From: b29396@freescale.com (Dong Aisheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/8] mmc: sdhci-esdhc-imx: fix reading cap_1 register value for mx6sl
Date: Fri, 18 Oct 2013 18:54:15 +0800 [thread overview]
Message-ID: <1382093661-4074-3-git-send-email-b29396@freescale.com> (raw)
In-Reply-To: <1382093661-4074-1-git-send-email-b29396@freescale.com>
When reading CAP_1 register for mx6sl, ignore bit[0-15] as it stores
CAP_2 register value which is new introduced in mx6sl.
Without this fix, the max clock for mx6sl may not be correct since
it's wrongly calculated by reading CAP_1 register.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index a4e0e3b..52c0760 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -226,6 +226,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
}
if (unlikely(reg == SDHCI_CAPABILITIES)) {
+ /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
+ if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
+ val &= 0xffff0000;
+
/* In FSL esdhc IC module, only bit20 is used to indicate the
* ADMA2 capability of esdhc, but this bit is messed up on
* some SOCs (e.g. on MX25, MX35 this bit is set, but they
--
1.7.2.rc3
next prev parent reply other threads:[~2013-10-18 10:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-18 10:54 [PATCH v2 0/8] mmc: sdhci-esdhc-imx: add std tuning for mx6sl and DDR mode support Dong Aisheng
2013-10-18 10:54 ` [PATCH v2 1/8] mmc: sdhci-esdhc-imx: add std tuning support for mx6sl Dong Aisheng
2013-10-18 11:33 ` Shawn Guo
2013-10-18 11:18 ` Dong Aisheng
2013-10-18 10:54 ` Dong Aisheng [this message]
2013-10-18 10:54 ` [PATCH v2 3/8] mmc: sdhci: report error once the maximum tuning loops exhausted or timeout Dong Aisheng
2013-10-18 10:54 ` [PATCH v2 4/8] mmc: sdhci-esdhc-imx: add DDR mode support for mx6 Dong Aisheng
2013-10-18 10:54 ` [PATCH v2 5/8] mmc: sdhci-esdhc-imx: add delay line setting support Dong Aisheng
2013-10-18 11:42 ` Shawn Guo
2013-10-18 11:30 ` Dong Aisheng
2013-10-18 11:57 ` Shawn Guo
2013-10-18 11:41 ` Dong Aisheng
2013-10-18 10:54 ` [PATCH v2 6/8] mmc: sdhci-esdhc-imx: enable SDR50 tuning for imx6q/dl Dong Aisheng
2013-10-18 10:54 ` [PATCH v2 7/8] mmc: sdhci-esdhc-imx: add preset value quirk for mx6 Dong Aisheng
2013-10-18 10:54 ` [PATCH v2 8/8] mmc: sdhci: remove unneeded call when have preset value quirk Dong Aisheng
2013-10-18 11:46 ` [PATCH v2 0/8] mmc: sdhci-esdhc-imx: add std tuning for mx6sl and DDR mode support Shawn Guo
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