[PATCH 0/2] can + ARM i.MX53: use 24 MHz clock parent on i.MX53

[PATCH 0/2] can + ARM i.MX53: use 24 MHz clock parent on i.MX53

[Marc Kleine-Budde]

Hello,

this series first fixes a bug in the flexcan driver, using the wrong clock for
the bit rate calculcation. The next patch switches the peripheral clock on
i.MX53 to lp_apm, which has a rate of 24 MHz. This is optimal for the CIA
recommended bit rates.

Tested on TQ's mba53 and mba6x [1].

Who is taking the series? Due to Lucas' patch:

    0a5b8df clk: imx5: introduce DT includes for clock provider

this series does not yet apply to my upstream (net-next/mastet).

Marc

[1] On i.MX6 the following patch is needed (which is already in Shawn's
    for-next):

    9b3d423 ARM: i.MX6q: fix the wrong parent of can_root clock

[PATCH 1/2] can: flexcan: use correct clock as base for bit rate calculation

[Marc Kleine-Budde]

The flexcan IP core uses the peripheral clock ("per") as basic clock for the
bit timing calculation. However the driver uses the the wrong clock ("ipg").
This leads to wrong bit rates if the rates on both clock are different.

This patch fixes the problem by using the correct clock for the bit rate
calculation.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/flexcan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index ae08cf1..aaed97b 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -1020,13 +1020,13 @@ static int flexcan_probe(struct platform_device *pdev)
 			dev_err(&pdev->dev, "no ipg clock defined\n");
 			return PTR_ERR(clk_ipg);
 		}
-		clock_freq = clk_get_rate(clk_ipg);
 
 		clk_per = devm_clk_get(&pdev->dev, "per");
 		if (IS_ERR(clk_per)) {
 			dev_err(&pdev->dev, "no per clock defined\n");
 			return PTR_ERR(clk_per);
 		}
+		clock_freq = clk_get_rate(clk_per);
 	}
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- 
1.8.4.2

[PATCH 2/2] ARM i.MX5: set CAN peripheral clock to 24 MHz parent

[Marc Kleine-Budde]

This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.

In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx51-imx53.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index e349fd5..28f7f3f 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -306,6 +306,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	/* move usb phy clk to 24MHz */
 	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
 
+	/* move can bus clk to 24MHz */
+	clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
+
 	clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
 	clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
 	clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
-- 
1.8.4.2

Re: [PATCH 2/2] ARM i.MX5: set CAN peripheral clock to 24 MHz parent

[Alexander Shiyan]

> This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
> lp_apm clock, which has a rate of 24 MHz.
> 
> In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
> recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
> has a rate of 66.666 MHz which produces quite large bit rate errors.
> 
> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index e349fd5..28f7f3f 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -306,6 +306,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>  	/* move usb phy clk to 24MHz */
>  	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
>  
> +	/* move can bus clk to 24MHz */
> +	clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
> +
>  	clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
>  	clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
>  	clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
> -- 

Again, CAN is missing on i.MX51, so this should be moved from common_init function.

---

[PATCH 2/2] ARM i.MX5: set CAN peripheral clock to 24 MHz parent

[Marc Kleine-Budde]

On 11/25/2013 06:27 PM, Alexander Shiyan wrote:
>> This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
>> lp_apm clock, which has a rate of 24 MHz.
>>
>> In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
>> recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
>> has a rate of 66.666 MHz which produces quite large bit rate errors.
>>
>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
>> ---
>>  arch/arm/mach-imx/clk-imx51-imx53.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
>> index e349fd5..28f7f3f 100644
>> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
>> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
>> @@ -306,6 +306,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>>  	/* move usb phy clk to 24MHz */
>>  	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
>>  
>> +	/* move can bus clk to 24MHz */
>> +	clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
>> +
>>  	clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
>>  	clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
>>  	clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
>> -- 
> 
> Again, CAN is missing on i.MX51, so this should be moved from common_init function.

Doh, will fix.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
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