* [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27
@ 2013-11-30 5:08 Alexander Shiyan
2013-12-03 7:28 ` Shawn Guo
0 siblings, 1 reply; 5+ messages in thread
From: Alexander Shiyan @ 2013-11-30 5:08 UTC (permalink / raw)
To: linux-arm-kernel
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-imx/clk-pllv1.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index c1eaee3..d21d14c 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -18,6 +18,11 @@
*
* PLL clock version 1, found on i.MX1/21/25/27/31/35
*/
+
+#define MFN_BITS (10)
+#define MFN_SIGN (BIT(MFN_BITS - 1))
+#define MFN_MASK (MFN_SIGN - 1)
+
struct clk_pllv1 {
struct clk_hw hw;
void __iomem *base;
@@ -25,6 +30,11 @@ struct clk_pllv1 {
#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
+static inline bool mfn_is_negative(unsigned int mfn)
+{
+ return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
+}
+
static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
/*
* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
- * 2's complements number
+ * 2's complements number.
+ * On i.MX27 the bit 9 is the sign bit.
*/
- if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
- mfn_abs = 0x400 - mfn;
+ if (mfn_is_negative(mfn)) {
+ if (cpu_is_mx27())
+ mfn_abs = mfn & MFN_MASK;
+ else
+ mfn_abs = BIT(MFN_BITS) - mfn;
+ }
rate = parent_rate * 2;
rate /= pd + 1;
@@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
do_div(ll, mfd + 1);
- if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+ if (mfn_is_negative(mfn))
ll = -ll;
ll = (rate * mfi) + ll;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27
2013-11-30 5:08 [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27 Alexander Shiyan
@ 2013-12-03 7:28 ` Shawn Guo
0 siblings, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2013-12-03 7:28 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Nov 30, 2013 at 09:08:19AM +0400, Alexander Shiyan wrote:
> MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
> is a just sign bit. This patch makes different calculation for i.MX27.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Sascha,
Do you have any comment on the patch? Or can I get your Ack on it?
Shawn
> ---
> arch/arm/mach-imx/clk-pllv1.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
> index c1eaee3..d21d14c 100644
> --- a/arch/arm/mach-imx/clk-pllv1.c
> +++ b/arch/arm/mach-imx/clk-pllv1.c
> @@ -18,6 +18,11 @@
> *
> * PLL clock version 1, found on i.MX1/21/25/27/31/35
> */
> +
> +#define MFN_BITS (10)
> +#define MFN_SIGN (BIT(MFN_BITS - 1))
> +#define MFN_MASK (MFN_SIGN - 1)
> +
> struct clk_pllv1 {
> struct clk_hw hw;
> void __iomem *base;
> @@ -25,6 +30,11 @@ struct clk_pllv1 {
>
> #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
>
> +static inline bool mfn_is_negative(unsigned int mfn)
> +{
> + return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
> +}
> +
> static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> @@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
>
> /*
> * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
> - * 2's complements number
> + * 2's complements number.
> + * On i.MX27 the bit 9 is the sign bit.
> */
> - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
> - mfn_abs = 0x400 - mfn;
> + if (mfn_is_negative(mfn)) {
> + if (cpu_is_mx27())
> + mfn_abs = mfn & MFN_MASK;
> + else
> + mfn_abs = BIT(MFN_BITS) - mfn;
> + }
>
> rate = parent_rate * 2;
> rate /= pd + 1;
> @@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
>
> do_div(ll, mfd + 1);
>
> - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
> + if (mfn_is_negative(mfn))
> ll = -ll;
>
> ll = (rate * mfi) + ll;
> --
> 1.8.3.2
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27
@ 2013-11-10 9:34 Alexander Shiyan
2013-12-03 9:33 ` Sascha Hauer
2013-12-03 10:50 ` Shawn Guo
0 siblings, 2 replies; 5+ messages in thread
From: Alexander Shiyan @ 2013-11-10 9:34 UTC (permalink / raw)
To: linux-arm-kernel
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-imx/clk-pllv1.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index c1eaee3..d21d14c 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -18,6 +18,11 @@
*
* PLL clock version 1, found on i.MX1/21/25/27/31/35
*/
+
+#define MFN_BITS (10)
+#define MFN_SIGN (BIT(MFN_BITS - 1))
+#define MFN_MASK (MFN_SIGN - 1)
+
struct clk_pllv1 {
struct clk_hw hw;
void __iomem *base;
@@ -25,6 +30,11 @@ struct clk_pllv1 {
#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
+static inline bool mfn_is_negative(unsigned int mfn)
+{
+ return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
+}
+
static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
/*
* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
- * 2's complements number
+ * 2's complements number.
+ * On i.MX27 the bit 9 is the sign bit.
*/
- if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
- mfn_abs = 0x400 - mfn;
+ if (mfn_is_negative(mfn)) {
+ if (cpu_is_mx27())
+ mfn_abs = mfn & MFN_MASK;
+ else
+ mfn_abs = BIT(MFN_BITS) - mfn;
+ }
rate = parent_rate * 2;
rate /= pd + 1;
@@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
do_div(ll, mfd + 1);
- if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+ if (mfn_is_negative(mfn))
ll = -ll;
ll = (rate * mfi) + ll;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27
2013-11-10 9:34 Alexander Shiyan
@ 2013-12-03 9:33 ` Sascha Hauer
2013-12-03 10:50 ` Shawn Guo
1 sibling, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2013-12-03 9:33 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 10, 2013 at 01:34:49PM +0400, Alexander Shiyan wrote:
> MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
> is a just sign bit. This patch makes different calculation for i.MX27.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
> ---
> arch/arm/mach-imx/clk-pllv1.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
> index c1eaee3..d21d14c 100644
> --- a/arch/arm/mach-imx/clk-pllv1.c
> +++ b/arch/arm/mach-imx/clk-pllv1.c
> @@ -18,6 +18,11 @@
> *
> * PLL clock version 1, found on i.MX1/21/25/27/31/35
> */
> +
> +#define MFN_BITS (10)
> +#define MFN_SIGN (BIT(MFN_BITS - 1))
> +#define MFN_MASK (MFN_SIGN - 1)
> +
> struct clk_pllv1 {
> struct clk_hw hw;
> void __iomem *base;
> @@ -25,6 +30,11 @@ struct clk_pllv1 {
>
> #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
>
> +static inline bool mfn_is_negative(unsigned int mfn)
> +{
> + return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
> +}
> +
> static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> @@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
>
> /*
> * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
> - * 2's complements number
> + * 2's complements number.
> + * On i.MX27 the bit 9 is the sign bit.
> */
> - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
> - mfn_abs = 0x400 - mfn;
> + if (mfn_is_negative(mfn)) {
> + if (cpu_is_mx27())
> + mfn_abs = mfn & MFN_MASK;
> + else
> + mfn_abs = BIT(MFN_BITS) - mfn;
> + }
>
> rate = parent_rate * 2;
> rate /= pd + 1;
> @@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
>
> do_div(ll, mfd + 1);
>
> - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
> + if (mfn_is_negative(mfn))
> ll = -ll;
>
> ll = (rate * mfi) + ll;
> --
> 1.8.1.5
>
>
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27
2013-11-10 9:34 Alexander Shiyan
2013-12-03 9:33 ` Sascha Hauer
@ 2013-12-03 10:50 ` Shawn Guo
1 sibling, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2013-12-03 10:50 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 10, 2013 at 01:34:49PM +0400, Alexander Shiyan wrote:
> MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
> is a just sign bit. This patch makes different calculation for i.MX27.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Applied, thanks.
^ permalink raw reply [flat|nested] 5+ messages in thread
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