[PATCH v3 00/10] ARM: sa1100: improve irq handling

[PATCH v3 00/10] ARM: sa1100: improve irq handling

[Dmitry Eremin-Solenikov]

Hello,

Please review my third attempts on touching the sa1100 irq code. I have split
changes to a serie of small, simple and easy to review patches, with each one
touching only one aspect of irq handling code for sa1100.

----------------------------------------------------------------
Dmitry Eremin-Solenikov (10):
      ARM: sa1100: switch to MULTI_IRQ_HANDLER
      ARM: sa1100: drop entry-macro.S
      ARM: sa1100: add platform functions to handle PWER settings
      arm: sa1100: use new functions that hide PWER access
      arm: sa1100: use ioremap'ped access instead of direct register access
      ARM: sa1100: enable IRQ domains
      arm: sa1100: introduce irqdomains support
      arm: sa1100: merge IRQ 11 to "normal" irq domain
      arm: sa1100: switch to hwirq usage
      ARM: locomo: don't clobber chip data for chained irq

 arch/arm/Kconfig                                |   2 +
 arch/arm/common/locomo.c                        |   4 +-
 arch/arm/mach-sa1100/generic.c                  |  21 ++
 arch/arm/mach-sa1100/generic.h                  |   2 +
 arch/arm/mach-sa1100/include/mach/entry-macro.S |  41 ----
 arch/arm/mach-sa1100/irq.c                      | 263 ++++++++++++++++--------
 6 files changed, 209 insertions(+), 124 deletions(-)
 delete mode 100644 arch/arm/mach-sa1100/include/mach/entry-macro.S

[PATCH v3 01/10] ARM: sa1100: switch to MULTI_IRQ_HANDLER

[Dmitry Eremin-Solenikov]

Add sa1100_handle_irq implementating handle_irq for sa1100 platform.
It is more or less a translation of old assembly code from assembler to
plain C. Alsi install this irq handler from sa1100_init_irq().

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/Kconfig           |  1 +
 arch/arm/mach-sa1100/irq.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c1f1a7e..14e907e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -693,6 +693,7 @@ config ARCH_SA1100
 	select GENERIC_CLOCKEVENTS
 	select HAVE_IDE
 	select ISA
+	select MULTI_IRQ_HANDLER
 	select NEED_MACH_MEMORY_H
 	select SPARSE_IRQ
 	help
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 2124f1fc..68e8f9d 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -20,6 +20,7 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <asm/mach/irq.h>
+#include <asm/exception.h>
 
 #include "generic.h"
 
@@ -291,6 +292,23 @@ static int __init sa1100irq_init_devicefs(void)
 
 device_initcall(sa1100irq_init_devicefs);
 
+static asmlinkage void __exception_irq_entry
+sa1100_handle_irq(struct pt_regs *regs)
+{
+	uint32_t icip, icmr, mask;
+
+	do {
+		icip = (ICIP);
+		icmr = (ICMR);
+		mask = icip & icmr;
+
+		if (mask == 0)
+			break;
+
+		handle_IRQ(fls(mask) - 1, regs);
+	} while (1);
+}
+
 void __init sa1100_init_irq(void)
 {
 	unsigned int irq;
@@ -338,5 +356,7 @@ void __init sa1100_init_irq(void)
 	irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
 	irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 
+	set_handle_irq(sa1100_handle_irq);
+
 	sa1100_init_gpio();
 }
-- 
1.8.5.1

[PATCH v3 02/10] ARM: sa1100: drop entry-macro.S

[Dmitry Eremin-Solenikov]

From: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>

As mach-sa1100 was converted to MULTI_IRQ_HANDLER, drop now-unused
entry-macro.S file.

Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>
---
 arch/arm/mach-sa1100/include/mach/entry-macro.S | 41 -------------------------
 1 file changed, 41 deletions(-)
 delete mode 100644 arch/arm/mach-sa1100/include/mach/entry-macro.S

diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
deleted file mode 100644
index 8cf7630..0000000
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for SA1100-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-		.macro  get_irqnr_preamble, base, tmp
-		mov	\base, #0xfa000000		@ ICIP = 0xfa050000
-		add	\base, \base, #0x00050000
-		.endm
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\irqstat, [\base]		@ get irqs
-		ldr	\irqnr, [\base, #4]		@ ICMR = 0xfa050004
-		ands	\irqstat, \irqstat, \irqnr
-		mov	\irqnr, #0
-		beq	1001f
-		tst	\irqstat, #0xff
-		moveq	\irqstat, \irqstat, lsr #8
-		addeq	\irqnr, \irqnr, #8
-		tsteq	\irqstat, #0xff
-		moveq	\irqstat, \irqstat, lsr #8
-		addeq	\irqnr, \irqnr, #8
-		tsteq	\irqstat, #0xff
-		moveq	\irqstat, \irqstat, lsr #8
-		addeq	\irqnr, \irqnr, #8
-		tst	\irqstat, #0x0f
-		moveq	\irqstat, \irqstat, lsr #4
-		addeq	\irqnr, \irqnr, #4
-		tst	\irqstat, #0x03
-		moveq	\irqstat, \irqstat, lsr #2
-		addeq	\irqnr, \irqnr, #2
-		tst	\irqstat, #0x01
-		addeqs	\irqnr, \irqnr, #1
-1001:
-		.endm
-
-- 
1.8.5.1

[PATCH v3 03/10] ARM: sa1100: add platform functions to handle PWER settings

[Dmitry Eremin-Solenikov]

PWER settings logically belongs neither to GPIO nor to system IRQ code.
Add special functions to handle PWER (for GPIO and for system IRQs)
from platform code.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/generic.c | 21 +++++++++++++++++++++
 arch/arm/mach-sa1100/generic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index d4ea142..002fe6b 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -410,3 +410,24 @@ void sa1110_mb_enable(void)
 	local_irq_restore(flags);
 }
 
+int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
+{
+	if (on)
+		PWER |= 1 << gpio;
+	else
+		PWER &= ~(1 << gpio);
+
+	return 0;
+}
+
+int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
+{
+	if (irq != IRQ_RTCAlrm)
+		return -EINVAL;
+
+	if (on)
+		PWER |= PWER_RTC;
+	else
+		PWER &= ~PWER_RTC;
+	return 0;
+}
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 0d92e11..a002b95 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -12,6 +12,8 @@ extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
 extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
+extern int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on);
+extern int sa11x0_sc_set_wake(unsigned int irq, unsigned int on);
 
 #define SET_BANK(__nr,__start,__size) \
 	mi->bank[__nr].start = (__start), \
-- 
1.8.5.1

[PATCH v3 04/10] arm: sa1100: use new functions that hide PWER access

[Dmitry Eremin-Solenikov]

In order to continue cleaning up of the sa11x0 IRQ driver, split away
PWER setting. Now irq driver asks core to enable either irq wake event
or to enable GPIO wake event, instead of accessing PWER directly.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/irq.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 68e8f9d..341d296 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -33,6 +33,7 @@
 static int GPIO_IRQ_rising_edge;
 static int GPIO_IRQ_falling_edge;
 static int GPIO_IRQ_mask = (1 << 11) - 1;
+static int GPIO_IRQ_wake_mask;
 
 /*
  * To get the GPIO number from an IRQ number
@@ -91,10 +92,11 @@ static void sa1100_low_gpio_unmask(struct irq_data *d)
 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
 {
 	if (on)
-		PWER |= 1 << d->irq;
+		GPIO_IRQ_wake_mask |= BIT(d->irq);
 	else
-		PWER &= ~(1 << d->irq);
-	return 0;
+		GPIO_IRQ_wake_mask &= ~BIT(d->irq);
+
+	return sa11x0_gpio_set_wake(d->irq, on);
 }
 
 static struct irq_chip sa1100_low_gpio_chip = {
@@ -172,10 +174,11 @@ static void sa1100_high_gpio_unmask(struct irq_data *d)
 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
 {
 	if (on)
-		PWER |= GPIO11_27_MASK(d->irq);
+		GPIO_IRQ_wake_mask |= GPIO11_27_MASK(d->irq);
 	else
-		PWER &= ~GPIO11_27_MASK(d->irq);
-	return 0;
+		GPIO_IRQ_wake_mask &= ~GPIO11_27_MASK(d->irq);
+
+	return sa11x0_gpio_set_wake(GPIO_11_27_IRQ(d->irq), on);
 }
 
 static struct irq_chip sa1100_high_gpio_chip = {
@@ -206,14 +209,7 @@ static void sa1100_unmask_irq(struct irq_data *d)
  */
 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 {
-	if (d->irq == IRQ_RTCAlrm) {
-		if (on)
-			PWER |= PWER_RTC;
-		else
-			PWER &= ~PWER_RTC;
-		return 0;
-	}
-	return -EINVAL;
+	return sa11x0_sc_set_wake(d->irq, on);
 }
 
 static struct irq_chip sa1100_normal_chip = {
@@ -253,8 +249,8 @@ static int sa1100irq_suspend(void)
 	/*
 	 * Set the appropriate edges for wakeup.
 	 */
-	GRER = PWER & GPIO_IRQ_rising_edge;
-	GFER = PWER & GPIO_IRQ_falling_edge;
+	GRER = GPIO_IRQ_wake_mask & GPIO_IRQ_rising_edge;
+	GFER = GPIO_IRQ_wake_mask & GPIO_IRQ_falling_edge;
 	
 	/*
 	 * Clear any pending GPIO interrupts.
-- 
1.8.5.1

[PATCH v3 05/10] arm: sa1100: use ioremap'ped access instead of direct register access

[Dmitry Eremin-Solenikov]

Ioremap MMIO register regions and use readl/writel family of functions
to access IRQ and GPIO edge detection registers.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/irq.c | 127 +++++++++++++++++++++++++++++++--------------
 1 file changed, 89 insertions(+), 38 deletions(-)

diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 341d296..5b2e183 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -17,13 +17,26 @@
 #include <linux/ioport.h>
 #include <linux/syscore_ops.h>
 
-#include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
 
 #include "generic.h"
 
+static void __iomem *irq_regbase;
+
+#define ICIP_OFFSET	0x00  /* IC IRQ Pending reg.             */
+#define ICMR_OFFSET	0x04  /* IC Mask Reg.                    */
+#define ICLR_OFFSET	0x08  /* IC Level Reg.                   */
+#define ICCR_OFFSET	0x0C  /* IC Control Reg.                 */
+#define ICFP_OFFSET	0x10  /* IC FIQ Pending reg.             */
+#define ICPR_OFFSET	0x20  /* IC Pending Reg.                 */
+
+static void __iomem *gpio_regbase;
+
+#define GRER_OFFSET	0x10  /* GPIO Rising-Edge detect Reg.    */
+#define GFER_OFFSET	0x14  /* GPIO Falling-Edge detect Reg.   */
+#define GEDR_OFFSET	0x18  /* GPIO Edge Detect status Reg.    */
 
 /*
  * SA1100 GPIO edge detection for IRQs:
@@ -65,8 +78,10 @@ static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
 	} else
 		GPIO_IRQ_falling_edge &= ~mask;
 
-	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
-	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
+	writel_relaxed(GPIO_IRQ_rising_edge & GPIO_IRQ_mask,
+			gpio_regbase + GRER_OFFSET);
+	writel_relaxed(GPIO_IRQ_falling_edge & GPIO_IRQ_mask,
+			gpio_regbase + GFER_OFFSET);
 
 	return 0;
 }
@@ -76,17 +91,21 @@ static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
  */
 static void sa1100_low_gpio_ack(struct irq_data *d)
 {
-	GEDR = (1 << d->irq);
+	writel_relaxed((1 << d->irq), gpio_regbase + GEDR_OFFSET);
 }
 
 static void sa1100_low_gpio_mask(struct irq_data *d)
 {
-	ICMR &= ~(1 << d->irq);
+	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
+	r &= ~BIT(d->irq);
+	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 static void sa1100_low_gpio_unmask(struct irq_data *d)
 {
-	ICMR |= 1 << d->irq;
+	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
+	r |= BIT(d->irq);
+	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
@@ -118,13 +137,13 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 {
 	unsigned int mask;
 
-	mask = GEDR & 0xfffff800;
+	mask = readl_relaxed(gpio_regbase + GEDR_OFFSET) & 0xfffff800;
 	do {
 		/*
 		 * clear down all currently active IRQ sources.
 		 * We will be processing them all.
 		 */
-		GEDR = mask;
+		writel_relaxed(mask, gpio_regbase + GEDR_OFFSET);
 
 		irq = IRQ_GPIO11;
 		mask >>= 11;
@@ -135,7 +154,7 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 			irq++;
 		} while (mask);
 
-		mask = GEDR & 0xfffff800;
+		mask = readl_relaxed(gpio_regbase + GEDR_OFFSET) & 0xfffff800;
 	} while (mask);
 }
 
@@ -148,17 +167,22 @@ static void sa1100_high_gpio_ack(struct irq_data *d)
 {
 	unsigned int mask = GPIO11_27_MASK(d->irq);
 
-	GEDR = mask;
+	writel_relaxed(mask, gpio_regbase + GEDR_OFFSET);
 }
 
 static void sa1100_high_gpio_mask(struct irq_data *d)
 {
 	unsigned int mask = GPIO11_27_MASK(d->irq);
+	unsigned int r;
 
 	GPIO_IRQ_mask &= ~mask;
 
-	GRER &= ~mask;
-	GFER &= ~mask;
+	r = readl_relaxed(gpio_regbase + GRER_OFFSET);
+	r &= ~mask;
+	writel_relaxed(r, gpio_regbase + GRER_OFFSET);
+	r = readl_relaxed(gpio_regbase + GFER_OFFSET);
+	r &= ~mask;
+	writel_relaxed(r, gpio_regbase + GFER_OFFSET);
 }
 
 static void sa1100_high_gpio_unmask(struct irq_data *d)
@@ -167,8 +191,10 @@ static void sa1100_high_gpio_unmask(struct irq_data *d)
 
 	GPIO_IRQ_mask |= mask;
 
-	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
-	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
+	writel_relaxed(GPIO_IRQ_rising_edge & GPIO_IRQ_mask,
+			gpio_regbase + GRER_OFFSET);
+	writel_relaxed(GPIO_IRQ_falling_edge & GPIO_IRQ_mask,
+			gpio_regbase + GFER_OFFSET);
 }
 
 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
@@ -196,12 +222,16 @@ static struct irq_chip sa1100_high_gpio_chip = {
  */
 static void sa1100_mask_irq(struct irq_data *d)
 {
-	ICMR &= ~(1 << d->irq);
+	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
+	r &= ~BIT(d->irq);
+	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 static void sa1100_unmask_irq(struct irq_data *d)
 {
-	ICMR |= (1 << d->irq);
+	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
+	r |= BIT(d->irq);
+	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 /*
@@ -223,6 +253,9 @@ static struct irq_chip sa1100_normal_chip = {
 static struct resource irq_resource =
 	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 
+static struct resource gpio_resource =
+	DEFINE_RES_MEM_NAMED(0x90040000, 20, "gpios");
+
 static struct sa1100irq_state {
 	unsigned int	saved;
 	unsigned int	icmr;
@@ -235,27 +268,28 @@ static int sa1100irq_suspend(void)
 	struct sa1100irq_state *st = &sa1100irq_state;
 
 	st->saved = 1;
-	st->icmr = ICMR;
-	st->iclr = ICLR;
-	st->iccr = ICCR;
+	st->icmr = readl_relaxed(irq_regbase + ICMR_OFFSET);
+	st->iclr = readl_relaxed(irq_regbase + ICLR_OFFSET);
+	st->iccr = readl_relaxed(irq_regbase + ICCR_OFFSET);
 
 	/*
 	 * Disable all GPIO-based interrupts.
 	 */
-	ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
-		  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
-		  IC_GPIO1|IC_GPIO0);
+	writel_relaxed(st->icmr & ~0xfff, irq_regbase + ICMR_OFFSET);
 
 	/*
 	 * Set the appropriate edges for wakeup.
 	 */
-	GRER = GPIO_IRQ_wake_mask & GPIO_IRQ_rising_edge;
-	GFER = GPIO_IRQ_wake_mask & GPIO_IRQ_falling_edge;
+	writel_relaxed(GPIO_IRQ_wake_mask & GPIO_IRQ_rising_edge,
+			gpio_regbase + GRER_OFFSET);
+	writel_relaxed(GPIO_IRQ_wake_mask & GPIO_IRQ_falling_edge,
+			gpio_regbase + GFER_OFFSET);
 	
 	/*
 	 * Clear any pending GPIO interrupts.
 	 */
-	GEDR = GEDR;
+	writel_relaxed(readl_relaxed(gpio_regbase + GEDR_OFFSET),
+			gpio_regbase + GEDR_OFFSET);
 
 	return 0;
 }
@@ -265,13 +299,15 @@ static void sa1100irq_resume(void)
 	struct sa1100irq_state *st = &sa1100irq_state;
 
 	if (st->saved) {
-		ICCR = st->iccr;
-		ICLR = st->iclr;
+		writel_relaxed(st->iccr, irq_regbase + ICCR_OFFSET);
+		writel_relaxed(st->iclr, irq_regbase + ICLR_OFFSET);
 
-		GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
-		GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
+		writel_relaxed(GPIO_IRQ_rising_edge & GPIO_IRQ_mask,
+				gpio_regbase + GRER_OFFSET);
+		writel_relaxed(GPIO_IRQ_falling_edge & GPIO_IRQ_mask,
+				gpio_regbase + GFER_OFFSET);
 
-		ICMR = st->icmr;
+		writel_relaxed(st->icmr, irq_regbase + ICMR_OFFSET);
 	}
 }
 
@@ -294,8 +330,8 @@ sa1100_handle_irq(struct pt_regs *regs)
 	uint32_t icip, icmr, mask;
 
 	do {
-		icip = (ICIP);
-		icmr = (ICMR);
+		icip = readl_relaxed(irq_regbase + ICIP_OFFSET);
+		icmr = readl_relaxed(irq_regbase + ICMR_OFFSET);
 		mask = icip & icmr;
 
 		if (mask == 0)
@@ -310,23 +346,38 @@ void __init sa1100_init_irq(void)
 	unsigned int irq;
 
 	request_resource(&iomem_resource, &irq_resource);
+	request_resource(&iomem_resource, &gpio_resource);
+
+	irq_regbase = ioremap(irq_resource.start,
+			resource_size(&irq_resource));
+	if (!irq_regbase) {
+		pr_err("Can not remap IRQ registers!\n");
+		return;
+	}
+
+	gpio_regbase = ioremap(gpio_resource.start,
+			resource_size(&gpio_resource));
+	if (!gpio_regbase) {
+		pr_err("Can not remap IRQ registers!\n");
+		return;
+	}
 
 	/* disable all IRQs */
-	ICMR = 0;
+	writel_relaxed(0, irq_regbase + ICMR_OFFSET);
 
 	/* all IRQs are IRQ, not FIQ */
-	ICLR = 0;
+	writel_relaxed(0, irq_regbase + ICLR_OFFSET);
 
 	/* clear all GPIO edge detects */
-	GFER = 0;
-	GRER = 0;
-	GEDR = -1;
+	writel_relaxed(0, gpio_regbase + GFER_OFFSET);
+	writel_relaxed(0, gpio_regbase + GRER_OFFSET);
+	writel_relaxed(~0, gpio_regbase + GEDR_OFFSET);
 
 	/*
 	 * Whatever the doc says, this has to be set for the wait-on-irq
 	 * instruction to work... on a SA1100 rev 9 at least.
 	 */
-	ICCR = 1;
+	writel_relaxed(1, irq_regbase + ICCR_OFFSET);
 
 	for (irq = 0; irq <= 10; irq++) {
 		irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
-- 
1.8.5.1

[PATCH v3 06/10] ARM: sa1100: enable IRQ domains

[Dmitry Eremin-Solenikov]

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 14e907e..4cf644a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -692,6 +692,7 @@ config ARCH_SA1100
 	select CPU_SA1100
 	select GENERIC_CLOCKEVENTS
 	select HAVE_IDE
+	select IRQ_DOMAIN
 	select ISA
 	select MULTI_IRQ_HANDLER
 	select NEED_MACH_MEMORY_H
-- 
1.8.5.1

[PATCH v3 07/10] arm: sa1100: introduce irqdomains support

[Dmitry Eremin-Solenikov]

Use irqdomains to manage both system and GPIO interrupts on SA1100 SoC
family. This opens path to further cleanup and unification in sa1100 IRQ
drivers.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/irq.c | 78 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 61 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 5b2e183..bb3bdad 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/ioport.h>
 #include <linux/syscore_ops.h>
 
@@ -127,6 +128,23 @@ static struct irq_chip sa1100_low_gpio_chip = {
 	.irq_set_wake	= sa1100_low_gpio_wake,
 };
 
+static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
+				 handle_edge_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
+	.map = sa1100_low_gpio_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_low_gpio_irqdomain;
+
 /*
  * IRQ11 (GPIO11 through 27) handler.  We enter here with the
  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
@@ -216,6 +234,23 @@ static struct irq_chip sa1100_high_gpio_chip = {
 	.irq_set_wake	= sa1100_high_gpio_wake,
 };
 
+static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
+				 handle_edge_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
+	.map = sa1100_high_gpio_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_high_gpio_irqdomain;
+
 /*
  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  * this is for internal IRQs i.e. from 11 to 31.
@@ -250,6 +285,23 @@ static struct irq_chip sa1100_normal_chip = {
 	.irq_set_wake	= sa1100_set_wake,
 };
 
+static int sa1100_normal_irqdomain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
+				 handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+
+	return 0;
+}
+
+static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
+	.map = sa1100_normal_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_normal_irqdomain;
+
 static struct resource irq_resource =
 	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 
@@ -343,8 +395,6 @@ sa1100_handle_irq(struct pt_regs *regs)
 
 void __init sa1100_init_irq(void)
 {
-	unsigned int irq;
-
 	request_resource(&iomem_resource, &irq_resource);
 	request_resource(&iomem_resource, &gpio_resource);
 
@@ -379,23 +429,17 @@ void __init sa1100_init_irq(void)
 	 */
 	writel_relaxed(1, irq_regbase + ICCR_OFFSET);
 
-	for (irq = 0; irq <= 10; irq++) {
-		irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
-					 handle_edge_irq);
-		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	}
+	sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
+			11, 0, 0,
+			&sa1100_low_gpio_irqdomain_ops, NULL);
 
-	for (irq = 12; irq <= 31; irq++) {
-		irq_set_chip_and_handler(irq, &sa1100_normal_chip,
-					 handle_level_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
+	sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
+			20, 12, 12,
+			&sa1100_normal_irqdomain_ops, NULL);
 
-	for (irq = 32; irq <= 48; irq++) {
-		irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
-					 handle_edge_irq);
-		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	}
+	sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
+			17, 32, 11,
+			&sa1100_high_gpio_irqdomain_ops, NULL);
 
 	/*
 	 * Install handler for GPIO 11-27 edge detect interrupts
-- 
1.8.5.1

[PATCH v3 08/10] arm: sa1100: merge IRQ 11 to "normal" irq domain

[Dmitry Eremin-Solenikov]

IRQ 11 is a shared IRQ receiving IRQs from "high" GPIOs. It is still
handled by sa1100_normal_chip, so there is no point to exclude it from
"normal" irq domain. The IRQF_VALID flag set by domain map function will
be cleared by irq_set_chained_handler() internally.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/irq.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index bb3bdad..5c72062 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -434,7 +434,7 @@ void __init sa1100_init_irq(void)
 			&sa1100_low_gpio_irqdomain_ops, NULL);
 
 	sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
-			20, 12, 12,
+			21, 11, 11,
 			&sa1100_normal_irqdomain_ops, NULL);
 
 	sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
@@ -444,7 +444,6 @@ void __init sa1100_init_irq(void)
 	/*
 	 * Install handler for GPIO 11-27 edge detect interrupts
 	 */
-	irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
 	irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 
 	set_handle_irq(sa1100_handle_irq);
-- 
1.8.5.1

[PATCH v3 09/10] arm: sa1100: switch to hwirq usage

[Dmitry Eremin-Solenikov]

Switch internally to using hardware irq numbers (hwirq). In case of GPIO
interrupts, hwirq is equal to GPIO number. In case of system interrupts,
hwirq is equal to interrupt number in the interrupt controller.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/irq.c | 41 ++++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 5c72062..43287a5 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -49,20 +49,11 @@ static int GPIO_IRQ_falling_edge;
 static int GPIO_IRQ_mask = (1 << 11) - 1;
 static int GPIO_IRQ_wake_mask;
 
-/*
- * To get the GPIO number from an IRQ number
- */
-#define GPIO_11_27_IRQ(i)	((i) - 21)
-#define GPIO11_27_MASK(irq)	(1 << GPIO_11_27_IRQ(irq))
-
 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
 {
 	unsigned int mask;
 
-	if (d->irq <= 10)
-		mask = 1 << d->irq;
-	else
-		mask = GPIO11_27_MASK(d->irq);
+	mask = BIT(d->hwirq);
 
 	if (type == IRQ_TYPE_PROBE) {
 		if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
@@ -92,31 +83,31 @@ static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
  */
 static void sa1100_low_gpio_ack(struct irq_data *d)
 {
-	writel_relaxed((1 << d->irq), gpio_regbase + GEDR_OFFSET);
+	writel_relaxed(BIT(d->hwirq), gpio_regbase + GEDR_OFFSET);
 }
 
 static void sa1100_low_gpio_mask(struct irq_data *d)
 {
 	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
-	r &= ~BIT(d->irq);
+	r &= ~BIT(d->hwirq);
 	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 static void sa1100_low_gpio_unmask(struct irq_data *d)
 {
 	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
-	r |= BIT(d->irq);
+	r |= BIT(d->hwirq);
 	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
 {
 	if (on)
-		GPIO_IRQ_wake_mask |= BIT(d->irq);
+		GPIO_IRQ_wake_mask |= BIT(d->hwirq);
 	else
-		GPIO_IRQ_wake_mask &= ~BIT(d->irq);
+		GPIO_IRQ_wake_mask &= ~BIT(d->hwirq);
 
-	return sa11x0_gpio_set_wake(d->irq, on);
+	return sa11x0_gpio_set_wake(d->hwirq, on);
 }
 
 static struct irq_chip sa1100_low_gpio_chip = {
@@ -183,14 +174,14 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
  */
 static void sa1100_high_gpio_ack(struct irq_data *d)
 {
-	unsigned int mask = GPIO11_27_MASK(d->irq);
+	unsigned int mask = BIT(d->hwirq);
 
 	writel_relaxed(mask, gpio_regbase + GEDR_OFFSET);
 }
 
 static void sa1100_high_gpio_mask(struct irq_data *d)
 {
-	unsigned int mask = GPIO11_27_MASK(d->irq);
+	unsigned int mask = BIT(d->hwirq);
 	unsigned int r;
 
 	GPIO_IRQ_mask &= ~mask;
@@ -205,7 +196,7 @@ static void sa1100_high_gpio_mask(struct irq_data *d)
 
 static void sa1100_high_gpio_unmask(struct irq_data *d)
 {
-	unsigned int mask = GPIO11_27_MASK(d->irq);
+	unsigned int mask = BIT(d->hwirq);
 
 	GPIO_IRQ_mask |= mask;
 
@@ -218,11 +209,11 @@ static void sa1100_high_gpio_unmask(struct irq_data *d)
 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
 {
 	if (on)
-		GPIO_IRQ_wake_mask |= GPIO11_27_MASK(d->irq);
+		GPIO_IRQ_wake_mask |= BIT(d->hwirq);
 	else
-		GPIO_IRQ_wake_mask &= ~GPIO11_27_MASK(d->irq);
+		GPIO_IRQ_wake_mask &= ~BIT(d->hwirq);
 
-	return sa11x0_gpio_set_wake(GPIO_11_27_IRQ(d->irq), on);
+	return sa11x0_gpio_set_wake(d->hwirq, on);
 }
 
 static struct irq_chip sa1100_high_gpio_chip = {
@@ -258,14 +249,14 @@ static struct irq_domain *sa1100_high_gpio_irqdomain;
 static void sa1100_mask_irq(struct irq_data *d)
 {
 	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
-	r &= ~BIT(d->irq);
+	r &= ~BIT(d->hwirq);
 	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
 static void sa1100_unmask_irq(struct irq_data *d)
 {
 	unsigned int r = readl_relaxed(irq_regbase + ICMR_OFFSET);
-	r |= BIT(d->irq);
+	r |= BIT(d->hwirq);
 	writel_relaxed(r, irq_regbase + ICMR_OFFSET);
 }
 
@@ -274,7 +265,7 @@ static void sa1100_unmask_irq(struct irq_data *d)
  */
 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 {
-	return sa11x0_sc_set_wake(d->irq, on);
+	return sa11x0_sc_set_wake(d->hwirq, on);
 }
 
 static struct irq_chip sa1100_normal_chip = {
-- 
1.8.5.1

[PATCH v3 10/10] ARM: locomo: don't clobber chip data for chained irq

[Dmitry Eremin-Solenikov]

Currently locomo uses chip data to pass private data to chained irq
handler. Thus it clobbers the private data of the corresponding chip
(sa1100 or pxa). Make locomo use handler data for this purpose.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/common/locomo.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index b55c362..f26bd50 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = {
 
 static void locomo_handler(unsigned int irq, struct irq_desc *desc)
 {
-	struct locomo *lchip = irq_get_chip_data(irq);
+	struct locomo *lchip = irq_get_handler_data(irq);
 	int req, i;
 
 	/* Acknowledge the parent IRQ */
@@ -198,7 +198,7 @@ static void locomo_setup_irq(struct locomo *lchip)
 	 * Install handler for IRQ_LOCOMO_HW.
 	 */
 	irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
-	irq_set_chip_data(lchip->irq, lchip);
+	irq_set_handler_data(lchip->irq, lchip);
 	irq_set_chained_handler(lchip->irq, locomo_handler);
 
 	/* Install handlers for IRQ_LOCOMO_* */
-- 
1.8.5.1

[PATCH v3 00/10] ARM: sa1100: improve irq handling

[Linus Walleij]

On Sun, Dec 15, 2013 at 5:28 AM, Dmitry Eremin-Solenikov
<dbaryshkov@gmail.com> wrote:

> Please review my third attempts on touching the sa1100 irq code. I have split
> changes to a serie of small, simple and easy to review patches, with each one
> touching only one aspect of irq handling code for sa1100.

I've tested this series on the H3600 and it works flawlessly.

For the series:
Tested-by: Linus Walleij <linus.walleij@linaro.org>

I guess you best way forward it to put patches into Russell's
patch tracker or send him a pull request.

Yours,
Linus Walleij

[PATCH v3 00/10] ARM: sa1100: improve irq handling

[Dmitry Eremin-Solenikov]

Hello,

On Fri, Dec 20, 2013 at 1:25 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Sun, Dec 15, 2013 at 5:28 AM, Dmitry Eremin-Solenikov
> <dbaryshkov@gmail.com> wrote:
>
>> Please review my third attempts on touching the sa1100 irq code. I have split
>> changes to a serie of small, simple and easy to review patches, with each one
>> touching only one aspect of irq handling code for sa1100.
>
> I've tested this series on the H3600 and it works flawlessly.
>
> For the series:
> Tested-by: Linus Walleij <linus.walleij@linaro.org>

Thank you!

>
> I guess you best way forward it to put patches into Russell's
> patch tracker or send him a pull request.

Russell, would you review these patches here, or I'd better put them
to patch tracker?

-- 
With best wishes
Dmitry