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From: dbaryshkov@gmail.com (Dmitry Eremin-Solenikov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 07/10] arm: sa1100: introduce irqdomains support
Date: Sun, 15 Dec 2013 08:28:14 +0400	[thread overview]
Message-ID: <1387081697-21841-8-git-send-email-dbaryshkov@gmail.com> (raw)
In-Reply-To: <1387081697-21841-1-git-send-email-dbaryshkov@gmail.com>

Use irqdomains to manage both system and GPIO interrupts on SA1100 SoC
family. This opens path to further cleanup and unification in sa1100 IRQ
drivers.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 arch/arm/mach-sa1100/irq.c | 78 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 61 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 5b2e183..bb3bdad 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/ioport.h>
 #include <linux/syscore_ops.h>
 
@@ -127,6 +128,23 @@ static struct irq_chip sa1100_low_gpio_chip = {
 	.irq_set_wake	= sa1100_low_gpio_wake,
 };
 
+static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
+				 handle_edge_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
+	.map = sa1100_low_gpio_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_low_gpio_irqdomain;
+
 /*
  * IRQ11 (GPIO11 through 27) handler.  We enter here with the
  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
@@ -216,6 +234,23 @@ static struct irq_chip sa1100_high_gpio_chip = {
 	.irq_set_wake	= sa1100_high_gpio_wake,
 };
 
+static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
+				 handle_edge_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
+	.map = sa1100_high_gpio_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_high_gpio_irqdomain;
+
 /*
  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  * this is for internal IRQs i.e. from 11 to 31.
@@ -250,6 +285,23 @@ static struct irq_chip sa1100_normal_chip = {
 	.irq_set_wake	= sa1100_set_wake,
 };
 
+static int sa1100_normal_irqdomain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
+				 handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+
+	return 0;
+}
+
+static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
+	.map = sa1100_normal_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_normal_irqdomain;
+
 static struct resource irq_resource =
 	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 
@@ -343,8 +395,6 @@ sa1100_handle_irq(struct pt_regs *regs)
 
 void __init sa1100_init_irq(void)
 {
-	unsigned int irq;
-
 	request_resource(&iomem_resource, &irq_resource);
 	request_resource(&iomem_resource, &gpio_resource);
 
@@ -379,23 +429,17 @@ void __init sa1100_init_irq(void)
 	 */
 	writel_relaxed(1, irq_regbase + ICCR_OFFSET);
 
-	for (irq = 0; irq <= 10; irq++) {
-		irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
-					 handle_edge_irq);
-		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	}
+	sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
+			11, 0, 0,
+			&sa1100_low_gpio_irqdomain_ops, NULL);
 
-	for (irq = 12; irq <= 31; irq++) {
-		irq_set_chip_and_handler(irq, &sa1100_normal_chip,
-					 handle_level_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
+	sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
+			20, 12, 12,
+			&sa1100_normal_irqdomain_ops, NULL);
 
-	for (irq = 32; irq <= 48; irq++) {
-		irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
-					 handle_edge_irq);
-		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-	}
+	sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
+			17, 32, 11,
+			&sa1100_high_gpio_irqdomain_ops, NULL);
 
 	/*
 	 * Install handler for GPIO 11-27 edge detect interrupts
-- 
1.8.5.1

  parent reply	other threads:[~2013-12-15  4:28 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-15  4:28 [PATCH v3 00/10] ARM: sa1100: improve irq handling Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 01/10] ARM: sa1100: switch to MULTI_IRQ_HANDLER Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 02/10] ARM: sa1100: drop entry-macro.S Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 03/10] ARM: sa1100: add platform functions to handle PWER settings Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 04/10] arm: sa1100: use new functions that hide PWER access Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 05/10] arm: sa1100: use ioremap'ped access instead of direct register access Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 06/10] ARM: sa1100: enable IRQ domains Dmitry Eremin-Solenikov
2013-12-15  4:28 ` Dmitry Eremin-Solenikov [this message]
2013-12-15  4:28 ` [PATCH v3 08/10] arm: sa1100: merge IRQ 11 to "normal" irq domain Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 09/10] arm: sa1100: switch to hwirq usage Dmitry Eremin-Solenikov
2013-12-15  4:28 ` [PATCH v3 10/10] ARM: locomo: don't clobber chip data for chained irq Dmitry Eremin-Solenikov
2013-12-20  9:25 ` [PATCH v3 00/10] ARM: sa1100: improve irq handling Linus Walleij
2013-12-20 11:15   ` Dmitry Eremin-Solenikov

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