* [PATCH RESEND] clk: divider: read before write for HIWORD mask
@ 2013-12-20 3:50 Haojian Zhuang
2013-12-20 8:18 ` Heiko Stübner
0 siblings, 1 reply; 2+ messages in thread
From: Haojian Zhuang @ 2013-12-20 3:50 UTC (permalink / raw)
To: linux-arm-kernel
When multiple dividers share one register, we need to read & mask
register fist. Then we set the right value.
For example, there're two mmc clock dividers shared in one registers.
The clock register is HIWORD type.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/clk/clk-divider.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8d3009e..e1ea289 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -227,12 +227,10 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->lock)
spin_lock_irqsave(divider->lock, flags);
- if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
- val = div_mask(divider) << (divider->shift + 16);
- } else {
- val = clk_readl(divider->reg);
- val &= ~(div_mask(divider) << divider->shift);
- }
+ val = clk_readl(divider->reg);
+ val &= ~(div_mask(divider) << divider->shift);
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK)
+ val |= div_mask(divider) << (divider->shift + 16);
val |= value << divider->shift;
clk_writel(val, divider->reg);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 2+ messages in thread* [PATCH RESEND] clk: divider: read before write for HIWORD mask
2013-12-20 3:50 [PATCH RESEND] clk: divider: read before write for HIWORD mask Haojian Zhuang
@ 2013-12-20 8:18 ` Heiko Stübner
0 siblings, 0 replies; 2+ messages in thread
From: Heiko Stübner @ 2013-12-20 8:18 UTC (permalink / raw)
To: linux-arm-kernel
Am Freitag, 20. Dezember 2013, 04:50:17 schrieb Haojian Zhuang:
> When multiple dividers share one register, we need to read & mask
> register fist. Then we set the right value.
>
> For example, there're two mmc clock dividers shared in one registers.
> The clock register is HIWORD type.
Why do you need the read before write on hiword registers?
Say you have the two dividers on bits [15:8] and [7:0]. When you change the
later one [7:0] you also set the bits [23:16] to enable the write to these
lower bits - but also only to them.
With this setting the other bits of the register you didn't mark for writing
won't be changed at all.
Heiko
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
> ---
> drivers/clk/clk-divider.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 8d3009e..e1ea289 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -227,12 +227,10 @@ static int clk_divider_set_rate(struct clk_hw *hw,
> unsigned long rate, if (divider->lock)
> spin_lock_irqsave(divider->lock, flags);
>
> - if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
> - val = div_mask(divider) << (divider->shift + 16);
> - } else {
> - val = clk_readl(divider->reg);
> - val &= ~(div_mask(divider) << divider->shift);
> - }
> + val = clk_readl(divider->reg);
> + val &= ~(div_mask(divider) << divider->shift);
> + if (divider->flags & CLK_DIVIDER_HIWORD_MASK)
> + val |= div_mask(divider) << (divider->shift + 16);
> val |= value << divider->shift;
> clk_writel(val, divider->reg);
^ permalink raw reply [flat|nested] 2+ messages in thread
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2013-12-20 8:18 ` Heiko Stübner
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