* [PATCH 2/6] ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module
2013-12-21 7:11 [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Alexander Shiyan
@ 2013-12-21 7:11 ` Alexander Shiyan
2013-12-21 7:11 ` [PATCH 3/6] ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC Alexander Shiyan
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Shiyan @ 2013-12-21 7:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch enables 1-Wire module for Phytec PCM-970 RDK.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 7ada054..eca1b6d 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -44,6 +44,10 @@
>;
};
+ pinctrl_owire1: owire1grp {
+ fsl,pins = <MX27_OWIRE1_PINGRP1>;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_UART1_PINGRP1
@@ -60,6 +64,12 @@
};
};
+&owire {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_owire1>;
+ status = "okay";
+};
+
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/6] ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC
2013-12-21 7:11 [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Alexander Shiyan
2013-12-21 7:11 ` [PATCH 2/6] ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module Alexander Shiyan
@ 2013-12-21 7:11 ` Alexander Shiyan
2013-12-21 7:11 ` [PATCH 4/6] ARM: dts: i.MX27: Add missing pullup settings for SDHC pin groups Alexander Shiyan
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Shiyan @ 2013-12-21 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Since SPI core does not use GPIO bindings for CS GPIOs,
we should add an active high level declaration.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 94ba726..c934999 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -61,8 +61,9 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13783";
- spi-max-frequency = <20000000>;
reg = <0>;
+ spi-cs-high;
+ spi-max-frequency = <20000000>;
interrupt-parent = <&gpio2>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-adc;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/6] ARM: dts: i.MX27: Add missing pullup settings for SDHC pin groups
2013-12-21 7:11 [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Alexander Shiyan
2013-12-21 7:11 ` [PATCH 2/6] ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module Alexander Shiyan
2013-12-21 7:11 ` [PATCH 3/6] ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC Alexander Shiyan
@ 2013-12-21 7:11 ` Alexander Shiyan
2013-12-21 7:11 ` [PATCH 5/6] ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC Alexander Shiyan
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Shiyan @ 2013-12-21 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/boot/dts/imx27-pingrp.h | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/imx27-pingrp.h b/arch/arm/boot/dts/imx27-pingrp.h
index 61eb710..57ca02f 100644
--- a/arch/arm/boot/dts/imx27-pingrp.h
+++ b/arch/arm/boot/dts/imx27-pingrp.h
@@ -101,28 +101,28 @@
MX27_PAD_PWMO__PWMO 0x0
#define MX27_SDHC1_PINGRP1 \
- MX27_PAD_SD1_CLK__SD1_CLK \
- MX27_PAD_SD1_CMD__SD1_CMD \
- MX27_PAD_SD1_D0__SD1_D0 \
- MX27_PAD_SD1_D1__SD1_D1 \
- MX27_PAD_SD1_D2__SD1_D2 \
- MX27_PAD_SD1_D3__SD1_D3
+ MX27_PAD_SD1_CLK__SD1_CLK 0x0 \
+ MX27_PAD_SD1_CMD__SD1_CMD 0x0 \
+ MX27_PAD_SD1_D0__SD1_D0 0x0 \
+ MX27_PAD_SD1_D1__SD1_D1 0x0 \
+ MX27_PAD_SD1_D2__SD1_D2 0x0 \
+ MX27_PAD_SD1_D3__SD1_D3 0x0
#define MX27_SDHC2_PINGRP1 \
- MX27_PAD_SD2_CLK__SD2_CLK \
- MX27_PAD_SD2_CMD__SD2_CMD \
- MX27_PAD_SD2_D0__SD2_D0 \
- MX27_PAD_SD2_D1__SD2_D1 \
- MX27_PAD_SD2_D2__SD2_D2 \
- MX27_PAD_SD2_D3__SD2_D3
+ MX27_PAD_SD2_CLK__SD2_CLK 0x0 \
+ MX27_PAD_SD2_CMD__SD2_CMD 0x0 \
+ MX27_PAD_SD2_D0__SD2_D0 0x0 \
+ MX27_PAD_SD2_D1__SD2_D1 0x0 \
+ MX27_PAD_SD2_D2__SD2_D2 0x0 \
+ MX27_PAD_SD2_D3__SD2_D3 0x0
#define MX27_SDHC3_PINGRP1 \
- MX27_PAD_SD3_CLK__SD3_CLK \
- MX27_PAD_SD3_CMD__SD3_CMD \
- MX27_PAD_SD3_D0__SD3_D0 \
- MX27_PAD_SD3_D1__SD3_D1 \
- MX27_PAD_SD3_D2__SD3_D2 \
- MX27_PAD_SD3_D3__SD3_D3
+ MX27_PAD_SD3_CLK__SD3_CLK 0x0 \
+ MX27_PAD_SD3_CMD__SD3_CMD 0x0 \
+ MX27_PAD_SD3_D0__SD3_D0 0x0 \
+ MX27_PAD_SD3_D1__SD3_D1 0x0 \
+ MX27_PAD_SD3_D2__SD3_D2 0x0 \
+ MX27_PAD_SD3_D3__SD3_D3 0x0
#define MX27_UART1_PINGRP1 \
MX27_PAD_UART1_TXD__UART1_TXD 0x0 \
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/6] ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC
2013-12-21 7:11 [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Alexander Shiyan
` (2 preceding siblings ...)
2013-12-21 7:11 ` [PATCH 4/6] ARM: dts: i.MX27: Add missing pullup settings for SDHC pin groups Alexander Shiyan
@ 2013-12-21 7:11 ` Alexander Shiyan
2013-12-21 7:11 ` [PATCH 6/6] ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM Alexander Shiyan
2013-12-23 7:53 ` [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Shawn Guo
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Shiyan @ 2013-12-21 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index eca1b6d..1967dad 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -48,6 +48,14 @@
fsl,pins = <MX27_OWIRE1_PINGRP1>;
};
+ pinctrl_sdhc2: sdhc2grp {
+ fsl,pins = <
+ MX27_SDHC2_PINGRP1
+ MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
+ MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_UART1_PINGRP1
@@ -71,6 +79,8 @@
};
&sdhci2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhc2>;
bus-width = <4>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 6/6] ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM
2013-12-21 7:11 [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Alexander Shiyan
` (3 preceding siblings ...)
2013-12-21 7:11 ` [PATCH 5/6] ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC Alexander Shiyan
@ 2013-12-21 7:11 ` Alexander Shiyan
2013-12-23 7:53 ` [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Shawn Guo
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Shiyan @ 2013-12-21 7:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds pinctrl definitions for WEIM CS4 and GPIO used as
CAN IRQ line.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 1967dad..eaaff00 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -69,6 +69,13 @@
MX27_UART2_RTSCTS_PINGRP1
>;
};
+
+ pinctrl_weim: weimgrp {
+ fsl,pins = <
+ MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */
+ MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */
+ >;
+ };
};
};
@@ -103,6 +110,9 @@
};
&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim>;
+
can at d4000000 {
compatible = "nxp,sja1000";
reg = <4 0x00000000 0x00000100>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group
2013-12-21 7:11 [PATCH 1/6] ARM: dts: imx27-phytec-phycore-som: Add NFC pin group Alexander Shiyan
` (4 preceding siblings ...)
2013-12-21 7:11 ` [PATCH 6/6] ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM Alexander Shiyan
@ 2013-12-23 7:53 ` Shawn Guo
5 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2013-12-23 7:53 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 21, 2013 at 11:11:37AM +0400, Alexander Shiyan wrote:
> This patch adds pin group fro NAND Flash Controller.
s/fro/for
I fixed it up and applied the series.
Shawn
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
> arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 6 ++++++
> arch/arm/boot/dts/imx27-pingrp.h | 9 +++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
> index 7087a4f..94ba726 100644
> --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
> +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
> @@ -201,10 +201,16 @@
> pinctrl_i2c2: i2c2grp {
> fsl,pins = <MX27_I2C2_PINGRP1>;
> };
> +
> + pinctrl_nfc: nfcgrp {
> + fsl,pins = <MX27_NFC_PINGRP1>;
> + };
> };
> };
>
> &nfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_nfc>;
> nand-bus-width = <8>;
> nand-ecc-mode = "hw";
> nand-on-flash-bbt;
> diff --git a/arch/arm/boot/dts/imx27-pingrp.h b/arch/arm/boot/dts/imx27-pingrp.h
> index edc1e90..61eb710 100644
> --- a/arch/arm/boot/dts/imx27-pingrp.h
> +++ b/arch/arm/boot/dts/imx27-pingrp.h
> @@ -85,6 +85,15 @@
> MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \
> MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>
> +#define MX27_NFC_PINGRP1 \
> + MX27_PAD_NFRB__NFRB 0x0 \
> + MX27_PAD_NFCLE__NFCLE 0x0 \
> + MX27_PAD_NFWP_B__NFWP_B 0x0 \
> + MX27_PAD_NFCE_B__NFCE_B 0x0 \
> + MX27_PAD_NFALE__NFALE 0x0 \
> + MX27_PAD_NFRE_B__NFRE_B 0x0 \
> + MX27_PAD_NFWE_B__NFWE_B 0x0
> +
> #define MX27_OWIRE1_PINGRP1 \
> MX27_PAD_RTCK__OWIRE 0x0
>
> --
> 1.8.3.2
>
^ permalink raw reply [flat|nested] 7+ messages in thread