From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C006CDB47C for ; Tue, 23 Jun 2026 22:35:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=oOrvEPgVQJ/jdeaFCbiFOH+3YX/7jM+3h5Opanbx+U8=; b=dpUfu4jV+B5hNuUwdUCfYBDqiN 769YaevWmS5fgSaLuGb7p5ZfgdDo8MRMVc9q9VYC7oK8l9mR0967tE4siSAbDL3L50ODDoxOETORn +pMzZJbxrDHI1o/dXRHzvNXyhHhz2kL5/s2dcMpY58K9XP0ydp9QlMUUXaigaeYRzPP2dF0rR7PBC EQF6+Hy+3CE2iD4ZjxIu2vt5P4bcpRmA2ZYiH4muqAjtHppVd1g8ac/x62m1+YFLsNLsbrRHFQWyK 20pzL1tiJKJ+ppkBRwtyemLiavNho9YC2bjRlqLjKFzE0Jm/laTuXznV9pNSawJA5gNrVNQZJN7/h u5M5d4sA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wc9iB-00000006wyE-10wy; Tue, 23 Jun 2026 22:35:19 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wc9i7-00000006wxk-0wSt; Tue, 23 Jun 2026 22:35:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B3EC1713; Tue, 23 Jun 2026 15:35:07 -0700 (PDT) Received: from [10.43.8.246] (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B3D423F632; Tue, 23 Jun 2026 15:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1782254112; bh=SRPt/Z1N9zfS5tVZtHc1Ym/DJpa09C6NIWLnEJarli8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=G5flbO5JtjY2PHGG2ojKGXX8SqI+2MRfa+r6LYez6kIYWrMO5mYm3Z02byPITyVx5 yIv7eGXrRte6UNWeKzB1Oryv66h5vXQEk1IcivwwfWgcjoIuMI/XRYk4euGrcbvraI pTYpub3JKKI8VTcq9p5Y59S2sQJTxCa6efj4jEfE= Message-ID: <138b5b54-7e2a-45fd-9c3f-eb4b4e04d954@arm.com> Date: Tue, 23 Jun 2026 23:35:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 5/8] clk: sunxi-ng: a733: Add bus clocks support To: Junhui Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> <20260310-a733-clk-v1-5-36b4e9b24457@pigmoral.tech> Content-Language: en-US From: Andre Przywara In-Reply-To: <20260310-a733-clk-v1-5-36b4e9b24457@pigmoral.tech> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260623_153515_433916_0EB914FD X-CRM114-Status: GOOD ( 26.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 3/10/26 08:33, Junhui Liu wrote: > Add the essential bus clocks in the Allwinner A733 CCU, including AHB, > APB0, APB1, APB_UART, NSI, and MBUS. These buses are necessary for many > other functional modules. Additionally clocks such as trace, gic and > cpu_peri are also added as they fall within the register address range > of the bus clocks, even though they are not strictly bus clocks. > > The MBUS clock is marked as critical to ensure the memory bus remains > operational at all times. For the NSI and MBUS clocks, the hardware > requires an update bit (bit 27) to be set so that the configuration > takes effect and the updated parameters can be correctly read back. > > Signed-off-by: Junhui Liu > --- > drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 131 +++++++++++++++++++++++++++++++++ > 1 file changed, 131 insertions(+) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c > index cf819504c51f..68457813dbbb 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c > +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c > @@ -19,6 +19,7 @@ > #include "ccu_common.h" > > #include "ccu_div.h" > +#include "ccu_mp.h" > #include "ccu_mult.h" > #include "ccu_nkmp.h" > #include "ccu_nm.h" > @@ -65,6 +66,16 @@ static const struct clk_hw *pll_ref_hws[] = { > &pll_ref_clk.common.hw > }; > > +/* > + * There is a non-software-configurable mux selecting between the DCXO and the > + * PLL_REF in hardware, whose output is fed to the sys-24M clock. Although both > + * sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor clock to > + * provide logical separation: > + * - pll-ref is dedicated to feeding other PLLs > + * - sys-24M serves as reference clock for downstream functional modules > + */ > +static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); > + > #define SUN60I_A733_PLL_DDR_REG 0x020 > static struct ccu_nkmp pll_ddr_clk = { > .enable = BIT(27), > @@ -371,6 +382,107 @@ static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, > static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, > SUN60I_A733_PLL_DE_REG, 16, 3, 0); > > +/************************************************************************** > + * bus clocks * > + **************************************************************************/ > + > +static const struct clk_parent_data ahb_apb_parents[] = { > + { .hw = &sys_24M_clk.hw }, > + { .fw_name = "losc" }, > + { .fw_name = "iosc" }, > + { .hw = &pll_periph0_600M_clk.hw }, > +}; > + > +static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500, > + 0, 5, /* M */ > + 24, 2, /* mux */ > + 0); > + > +static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, > + 0, 5, /* M */ > + 24, 2, /* mux */ > + 0); > + > +static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, > + 0, 5, /* M */ > + 24, 2, /* mux */ > + 0); > + > +static const struct clk_parent_data apb_uart_parents[] = { > + { .hw = &sys_24M_clk.hw }, > + { .fw_name = "losc" }, > + { .fw_name = "iosc" }, > + { .hw = &pll_periph0_600M_clk.hw }, > + { .hw = &pll_periph0_480M_clk.common.hw }, > +}; > +static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x538, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + 0); > + > +static const struct clk_parent_data trace_parents[] = { > + { .hw = &sys_24M_clk.hw }, > + { .fw_name = "losc" }, > + { .fw_name = "iosc" }, > + { .hw = &pll_periph0_300M_clk.hw }, > + { .hw = &pll_periph0_400M_clk.hw }, > +}; > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const struct clk_parent_data gic_cpu_peri_parents[] = { > + { .hw = &sys_24M_clk.hw }, > + { .fw_name = "losc" }, > + { .hw = &pll_periph0_600M_clk.hw }, > + { .hw = &pll_periph0_480M_clk.common.hw }, > + { .hw = &pll_periph0_400M_clk.hw }, > +}; > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gic_clk, "gic", gic_cpu_peri_parents, 0x560, Do we really want to model the GIC clock? The A523 has one as well, as we don't describe it there. And while the GICv3 binding describes a clock property, the Linux driver completely ignores that. So if I see this correctly, this clock would become unused, and would be turned off, killing the GIC? So we would at least need a CLK_IS_CRITICAL flag? But it's a good reminder to lift this clock to something PLL based, in U-Boot's SPL, because I guess the 24MHz are rather slow. > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(cpu_peri_clk, "cpu-peri", gic_cpu_peri_parents, 0x568, What is this clock about? I don't see it referenced by any peripheral in the manual. > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const struct clk_parent_data nsi_parents[] = { > + { .hw = &sys_24M_clk.hw }, > + { .hw = &pll_ddr_clk.common.hw }, > + { .hw = &pll_periph0_800M_clk.common.hw }, > + { .hw = &pll_periph0_600M_clk.hw }, > + { .hw = &pll_periph0_480M_clk.common.hw }, > + { .hw = &pll_de_3x_clk.common.hw }, > +}; > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(nsi_clk, "nsi", nsi_parents, 0x580, Similar question like for the GIC: do we need this in the kernel, and do we need to prevent this from being turned off? > + 0, 5, /* M */ > + 0, 0, /* no P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0, CCU_FEATURE_UPDATE_BIT); > + > +static const struct clk_parent_data mbus_parents[] = { > + { .hw = &sys_24M_clk.hw }, > + { .hw = &pll_periph1_600M_clk.hw }, > + { .hw = &pll_ddr_clk.common.hw }, > + { .hw = &pll_periph1_480M_clk.common.hw }, > + { .hw = &pll_periph1_400M_clk.hw }, > + { .hw = &pll_npu_clk.common.hw }, > +}; > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588, > + 0, 5, /* M */ > + 0, 0, /* no P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_IS_CRITICAL, > + CCU_FEATURE_UPDATE_BIT); > + > /* > * Contains all clocks that are controlled by a hardware register. They > * have a (sunxi) .common member, which needs to be initialised by the common > @@ -407,11 +519,21 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { > &pll_de_clk.common, > &pll_de_4x_clk.common, > &pll_de_3x_clk.common, > + &ahb_clk.common, > + &apb0_clk.common, > + &apb1_clk.common, > + &apb_uart_clk.common, > + &trace_clk.common, > + &gic_clk.common, > + &cpu_peri_clk.common, > + &nsi_clk.common, > + &mbus_clk.common, > }; > > static struct clk_hw_onecell_data sun60i_a733_hw_clks = { > .hws = { > [CLK_PLL_REF] = &pll_ref_clk.common.hw, > + [CLK_SYS_24M] = &sys_24M_clk.hw, > [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, > [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw, > [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw, > @@ -453,6 +575,15 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { > [CLK_PLL_DE] = &pll_de_clk.common.hw, > [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw, > [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw, > + [CLK_AHB] = &ahb_clk.common.hw, > + [CLK_APB0] = &apb0_clk.common.hw, > + [CLK_APB1] = &apb1_clk.common.hw, > + [CLK_APB_UART] = &apb_uart_clk.common.hw, > + [CLK_TRACE] = &trace_clk.common.hw, > + [CLK_GIC] = &gic_clk.common.hw, > + [CLK_CPU_PERI] = &cpu_peri_clk.common.hw, > + [CLK_NSI] = &nsi_clk.common.hw, > + [CLK_MBUS] = &mbus_clk.common.hw, > }, > .num = CLK_FANOUT3 + 1, > }; >