From mboxrd@z Thu Jan 1 00:00:00 1970 From: b.brezillon.dev@gmail.com (Boris BREZILLON) Date: Wed, 29 Jan 2014 15:34:17 +0100 Subject: =?UTF-8?q?=5BRFC=20PATCH=20v2=2007/14=5D=20of=3A=20mtd=3A=20add=20documentation=20for=20the=20ONFI=20NAND=20timing=20mode=20property?= In-Reply-To: <1391006064-28890-1-git-send-email-b.brezillon.dev@gmail.com> References: <1391006064-28890-1-git-send-email-b.brezillon.dev@gmail.com> Message-ID: <1391006064-28890-8-git-send-email-b.brezillon.dev@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add documentation for the ONFI NAND timing mode property. Signed-off-by: Boris BREZILLON --- Documentation/devicetree/bindings/mtd/nand.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt index 0c962296..75e46f3 100644 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ b/Documentation/devicetree/bindings/mtd/nand.txt @@ -8,3 +8,8 @@ E.g. : nand-ecc-level = <4 512>; /* 4 bits / 512 bytes */ - nand-bus-width : 8 or 16 bus width if not present 8 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false +- onfi,nand-timing-mode: an integer encoding the ONFI timing mode of the NAND + chip. This is only used when the chip does not support the ONFI standard. + Choose the closest mode fulfilling the NAND chip timings. + For a full description of the different timing modes see this document: + www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf? -- 1.7.9.5