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a=rsa-sha256; c=relaxed/relaxed; d=savoirfairelinux.com; s=DFC430D2-D198-11EC-948E-34200CB392D2; t=1706811893; bh=WUJ0xiWlw9xRPJdK54m22egoVgIAQyxZK6o/wNJkTao=; h=Date:From:To:Message-ID:MIME-Version; b=hAzdaJWDg2GDYPP84GxKXgMt+u9Q+eTH24HnnZ3OOfsteDUpEf1j770iBFYmQRhdv plPutFLy/rr9ALL8PW7mOzRNDIVdEs9IfwTQ3eplvR2tnlmHb/hs6YKlqghAKdf9L9 rM6xdQX75PelHtlALlZmSwcQDSt2TGVYu7SyebPOxtV7IYKR0FUGdfVxi+gfCmYPYz N6BkjRya3QqiVKmQuQdT6gBp01U5aOPPE2HUaEQC6MQaGPPjjdR/rWXS1139Ch/mrP UB4lAJ/kZ3ecowl0OQ24FjQ7tpoE8KbxBhgP2KTyhtfMLBWaTI+znDdHSJLupakSD6 iRl+y5SV3vvpA== X-Virus-Scanned: amavis at mail.savoirfairelinux.com Received: from mail.savoirfairelinux.com ([127.0.0.1]) by localhost (mail.savoirfairelinux.com [127.0.0.1]) (amavis, port 10026) with ESMTP id jciq3CuDmZsX; Thu, 1 Feb 2024 13:24:53 -0500 (EST) Received: from mail.savoirfairelinux.com (mail.savoirfairelinux.com [192.168.48.237]) by mail.savoirfairelinux.com (Postfix) with ESMTP id D9CC89C2B7A; Thu, 1 Feb 2024 13:24:52 -0500 (EST) Date: Thu, 1 Feb 2024 13:24:52 -0500 (EST) From: Charles Perry To: Krzysztof Kozlowski Cc: mdf , Allen VANDIVER , Brian CODY , hao wu , yilun xu , Tom Rix , Rob Herring , krzysztof kozlowski+dt , Conor Dooley , Michal Simek , linux-fpga , devicetree , linux-kernel , linux-arm-kernel@lists.infradead.org Message-ID: <1391244934.434321.1706811892834.JavaMail.zimbra@savoirfairelinux.com> In-Reply-To: References: <20240129225602.3832449-1-charles.perry@savoirfairelinux.com> <20240131230542.3993409-1-charles.perry@savoirfairelinux.com> <20240131230542.3993409-3-charles.perry@savoirfairelinux.com> Subject: Re: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema MIME-Version: 1.0 X-Mailer: Zimbra 8.8.15_GA_4581 (ZimbraWebClient - FF120 (Linux)/8.8.15_GA_4581) Thread-Topic: dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Thread-Index: aG2eE2gfRdKUBYCYyXilt6Ey1bVw9w== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_102457_964683_3E80360D X-CRM114-Status: GOOD ( 16.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ----- On Feb 1, 2024, at 3:07 AM, Krzysztof Kozlowski krzysztof.kozlowski@linaro.org wrote: > On 01/02/2024 00:05, Charles Perry wrote: >> Document the slave SelectMAP interface of Xilinx 7 series FPGA. >> >> Signed-off-by: Charles Perry >> --- >> .../bindings/fpga/xlnx,fpga-selectmap.yaml | 83 +++++++++++++++++++ >> 1 file changed, 83 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> >> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> new file mode 100644 >> index 0000000000000..c9a446b43cdd9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> @@ -0,0 +1,83 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx SelectMAP FPGA interface >> + >> +maintainers: >> + - Charles Perry >> + >> +description: | >> + Xilinx 7 Series FPGAs support a method of loading the bitstream over a >> + parallel port named the SelectMAP interface in the documentation. Only >> + the x8 mode is supported where data is loaded at one byte per rising edge of >> + the clock, with the MSB of each byte presented to the D0 pin. >> + >> + Datasheets: >> + >> https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf >> + >> +allOf: >> + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# >> + >> +properties: >> + compatible: >> + enum: >> + - xlnx,fpga-selectmap > > Your description mentions "7 Series" which is not present in compatible > and title. What is exactly the product here? Interface usually is not > the final binding, so is this specific to some particular FPGA or SoC? > > > Best regards, > Krzysztof This is specific to the FPGA, the 7 series encompass the following part family: * Spartan-7 (XC7S6, XC7S15, ... XC7S100) * Artix-7 (XC7A12T, XC7A15T, ... XC7A200T) * Kintex-7 (XC7K70T, XC7K160T, ... XC7K480T) * Virtex-7 (XC7V585T, XC7V2000T, XC7VX330T, XC7VX415T, ... XC7VX1140T, XC7VH580T, XC7VH870T) The configuration guide of Xilinx [1] tells us that all those devices share a common programming scheme. I do agree that having a mention of "7 series" in the compatible name would be beneficial as Xilinx has more FPGA than just the 7 series. The name was inspired from "xlnx,fpga-slave-serial" which is the compatible for the serial interface. What about "xlnx,fpga-xc7-selectmap" ? I'm also seeing that I missed some mention of the "slave" word in the commit message, will fix. Regards, Charles [1] https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel