* [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits
2014-02-07 15:21 [PATCH v4 0/5] clk: sunxi usb clks support Hans de Goede
@ 2014-02-07 15:21 ` Hans de Goede
2014-02-07 16:27 ` Philipp Zabel
2014-02-07 19:30 ` Maxime Ripard
2014-02-07 15:21 ` [PATCH v4 2/5] clk: sunxi: Add USB clock register defintions Hans de Goede
` (4 subsequent siblings)
5 siblings, 2 replies; 11+ messages in thread
From: Hans de Goede @ 2014-02-07 15:21 UTC (permalink / raw)
To: linux-arm-kernel
The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 64bda21..1e15e4c 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -18,6 +18,7 @@
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/reset-controller.h>
#include "clk-factors.h"
@@ -838,6 +839,59 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
/**
+ * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
+ */
+
+struct gates_reset_data {
+ void __iomem *reg;
+ spinlock_t *lock;
+ struct reset_controller_dev rcdev;
+};
+
+static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct gates_reset_data *data = container_of(rcdev,
+ struct gates_reset_data,
+ rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(data->lock, flags);
+
+ reg = readl(data->reg);
+ writel(reg & ~BIT(id), data->reg);
+
+ spin_unlock_irqrestore(data->lock, flags);
+
+ return 0;
+}
+
+static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct gates_reset_data *data = container_of(rcdev,
+ struct gates_reset_data,
+ rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(data->lock, flags);
+
+ reg = readl(data->reg);
+ writel(reg | BIT(id), data->reg);
+
+ spin_unlock_irqrestore(data->lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops sunxi_gates_reset_ops = {
+ .assert = sunxi_gates_reset_assert,
+ .deassert = sunxi_gates_reset_deassert,
+};
+
+/**
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
*/
@@ -845,6 +899,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
+ u32 reset_mask;
};
static const struct gates_data sun4i_axi_gates_data __initconst = {
@@ -915,6 +970,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
struct gates_data *data)
{
struct clk_onecell_data *clk_data;
+ struct gates_reset_data *reset_data;
const char *clk_parent;
const char *clk_name;
void *reg;
@@ -958,6 +1014,21 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
clk_data->clk_num = i;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ /* Register a reset controler for gates with reset bits */
+ if (data->reset_mask == 0)
+ return;
+
+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+ if (!reset_data)
+ return;
+
+ reset_data->reg = reg;
+ reset_data->lock = &clk_lock;
+ reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
+ reset_data->rcdev.ops = &sunxi_gates_reset_ops;
+ reset_data->rcdev.of_node = node;
+ reset_controller_register(&reset_data->rcdev);
}
--
1.8.4.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits
2014-02-07 15:21 ` [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits Hans de Goede
@ 2014-02-07 16:27 ` Philipp Zabel
2014-02-07 19:30 ` Maxime Ripard
1 sibling, 0 replies; 11+ messages in thread
From: Philipp Zabel @ 2014-02-07 16:27 UTC (permalink / raw)
To: linux-arm-kernel
Am Freitag, den 07.02.2014, 16:21 +0100 schrieb Hans de Goede:
> The usb-clk register is special in that it not only contains clk gate bits,
> but also has a few reset bits. This commit adds support for this by allowing
> gates type sunxi clks to also register a reset controller.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 64bda21..1e15e4c 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -18,6 +18,7 @@
> #include <linux/clkdev.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> +#include <linux/reset-controller.h>
>
> #include "clk-factors.h"
>
> @@ -838,6 +839,59 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>
>
> /**
> + * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
> + */
> +
> +struct gates_reset_data {
> + void __iomem *reg;
> + spinlock_t *lock;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct gates_reset_data *data = container_of(rcdev,
> + struct gates_reset_data,
> + rcdev);
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(data->lock, flags);
> +
> + reg = readl(data->reg);
> + writel(reg & ~BIT(id), data->reg);
> +
> + spin_unlock_irqrestore(data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct gates_reset_data *data = container_of(rcdev,
> + struct gates_reset_data,
> + rcdev);
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(data->lock, flags);
> +
> + reg = readl(data->reg);
> + writel(reg | BIT(id), data->reg);
> +
> + spin_unlock_irqrestore(data->lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops sunxi_gates_reset_ops = {
> + .assert = sunxi_gates_reset_assert,
> + .deassert = sunxi_gates_reset_deassert,
> +};
> +
> +/**
> * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
> */
>
> @@ -845,6 +899,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>
> struct gates_data {
> DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> + u32 reset_mask;
> };
>
> static const struct gates_data sun4i_axi_gates_data __initconst = {
> @@ -915,6 +970,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
> struct gates_data *data)
> {
> struct clk_onecell_data *clk_data;
> + struct gates_reset_data *reset_data;
> const char *clk_parent;
> const char *clk_name;
> void *reg;
> @@ -958,6 +1014,21 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
> clk_data->clk_num = i;
>
> of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + /* Register a reset controler for gates with reset bits */
> + if (data->reset_mask == 0)
> + return;
> +
> + reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
> + if (!reset_data)
> + return;
> +
> + reset_data->reg = reg;
> + reset_data->lock = &clk_lock;
> + reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
> + reset_data->rcdev.ops = &sunxi_gates_reset_ops;
> + reset_data->rcdev.of_node = node;
> + reset_controller_register(&reset_data->rcdev);
> }
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits
2014-02-07 15:21 ` [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits Hans de Goede
2014-02-07 16:27 ` Philipp Zabel
@ 2014-02-07 19:30 ` Maxime Ripard
1 sibling, 0 replies; 11+ messages in thread
From: Maxime Ripard @ 2014-02-07 19:30 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Feb 07, 2014 at 04:21:49PM +0100, Hans de Goede wrote:
> The usb-clk register is special in that it not only contains clk gate bits,
> but also has a few reset bits. This commit adds support for this by allowing
> gates type sunxi clks to also register a reset controller.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140207/eb93acaa/attachment-0001.sig>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 2/5] clk: sunxi: Add USB clock register defintions
2014-02-07 15:21 [PATCH v4 0/5] clk: sunxi usb clks support Hans de Goede
2014-02-07 15:21 ` [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits Hans de Goede
@ 2014-02-07 15:21 ` Hans de Goede
2014-02-07 19:29 ` Maxime Ripard
2014-02-07 15:21 ` [PATCH v4 3/5] ARM: sun4i: dt: Add bindings for USB clocks Hans de Goede
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Hans de Goede @ 2014-02-07 15:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Roman Byshko <rbyshko@gmail.com>
Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 +++++
drivers/clk/sunxi/clk-sunxi.c | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 27f19f1..5aa8d6d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -38,6 +38,8 @@ Required properties:
"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
+ "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
+ "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@@ -54,6 +56,9 @@ Required properties for all clocks:
For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
+And "allwinner,*-usb-clk" clocks also require:
+- reset-cells : shall be set to 1
+
Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 1e15e4c..61e57d2 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -910,6 +910,16 @@ static const struct gates_data sun4i_ahb_gates_data __initconst = {
.mask = {0x7F77FFF, 0x14FB3F},
};
+static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
+ .mask = {0x1C0},
+ .reset_mask = 0x07,
+};
+
+static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
+ .mask = {0x140},
+ .reset_mask = 0x03,
+};
+
static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
.mask = {0x147667e7, 0x185915},
};
@@ -1257,6 +1267,8 @@ static const struct of_device_id clk_gates_match[] __initconst = {
{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
+ {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
+ {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
{}
};
--
1.8.4.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 3/5] ARM: sun4i: dt: Add bindings for USB clocks
2014-02-07 15:21 [PATCH v4 0/5] clk: sunxi usb clks support Hans de Goede
2014-02-07 15:21 ` [PATCH v4 1/5] clk: sunxi: Add support for USB clock-register reset bits Hans de Goede
2014-02-07 15:21 ` [PATCH v4 2/5] clk: sunxi: Add USB clock register defintions Hans de Goede
@ 2014-02-07 15:21 ` Hans de Goede
2014-02-07 15:21 ` [PATCH v4 4/5] ARM: sun5i: " Hans de Goede
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Hans de Goede @ 2014-02-07 15:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ebb4cd0..8d10f27 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -301,6 +301,15 @@
clock-output-names = "ir1";
};
+ usb_clk: clk at 01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+ };
+
spi3_clk: clk at 01c200d4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
--
1.8.4.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 4/5] ARM: sun5i: dt: Add bindings for USB clocks
2014-02-07 15:21 [PATCH v4 0/5] clk: sunxi usb clks support Hans de Goede
` (2 preceding siblings ...)
2014-02-07 15:21 ` [PATCH v4 3/5] ARM: sun4i: dt: Add bindings for USB clocks Hans de Goede
@ 2014-02-07 15:21 ` Hans de Goede
2014-02-07 15:21 ` [PATCH v4 5/5] ARM: sun7i: " Hans de Goede
2014-02-18 14:42 ` [PATCH v4 0/5] clk: sunxi usb clks support Emilio López
5 siblings, 0 replies; 11+ messages in thread
From: Hans de Goede @ 2014-02-07 15:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 9 +++++++++
arch/arm/boot/dts/sun5i-a13.dtsi | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 38d01bd..2ed7429 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -264,6 +264,15 @@
clock-output-names = "ir0";
};
+ usb_clk: clk at 01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun5i-a13-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_phy";
+ };
+
mbus_clk: clk at 01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ddd39d3..30ece67 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -261,6 +261,15 @@
clock-output-names = "ir0";
};
+ usb_clk: clk at 01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun5i-a13-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_phy";
+ };
+
mbus_clk: clk at 01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
--
1.8.4.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 5/5] ARM: sun7i: dt: Add bindings for USB clocks
2014-02-07 15:21 [PATCH v4 0/5] clk: sunxi usb clks support Hans de Goede
` (3 preceding siblings ...)
2014-02-07 15:21 ` [PATCH v4 4/5] ARM: sun5i: " Hans de Goede
@ 2014-02-07 15:21 ` Hans de Goede
2014-02-18 14:42 ` [PATCH v4 0/5] clk: sunxi usb clks support Emilio López
5 siblings, 0 replies; 11+ messages in thread
From: Hans de Goede @ 2014-02-07 15:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 316cab8..14d9696 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -289,6 +289,15 @@
clock-output-names = "ir1";
};
+ usb_clk: clk at 01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+ };
+
spi3_clk: clk at 01c200d4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
--
1.8.4.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 0/5] clk: sunxi usb clks support
2014-02-07 15:21 [PATCH v4 0/5] clk: sunxi usb clks support Hans de Goede
` (4 preceding siblings ...)
2014-02-07 15:21 ` [PATCH v4 5/5] ARM: sun7i: " Hans de Goede
@ 2014-02-18 14:42 ` Emilio López
2014-02-18 15:50 ` Maxime Ripard
5 siblings, 1 reply; 11+ messages in thread
From: Emilio López @ 2014-02-18 14:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi Hans,
El 07/02/14 12:21, Hans de Goede escribi?:
> Hi All,
>
> And here is v4 of my sunxi usb clks support series.
>
> Changes since v2:
> -rename the compatibilty strings from foo-usb-gates-clk to foo-usb-clk
>
> Changes since v3:
> -rename the compatibilty string for sun4i-usb-clk to sun4i-a10-usb-clk
>
> Note the dts bits (patches 3-5) of this series depends on Chen-Yu Tsai's clk
> rename series.
>
> Emilio, should Mike pick patches 1-2 up directly, or should they go through
> your tree?
I have taken 1-2 on sunxi-clk-for-mike with acks from Maxime and Philipp.
> Maxime, can you please add patches 3-5 to your dts tree ? Assuming that
> wens clk rename patches are already there.
Maxime, please do :)
Cheers, and thanks for working on USB!
Emilio
^ permalink raw reply [flat|nested] 11+ messages in thread