[PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x

[PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x

[Lee Jones]

The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.

Cc: devicetree at vger.kernel.org
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
new file mode 100644
index 0000000..fdfa7ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
@@ -0,0 +1,43 @@
+STMicroelectronics STi MIPHY365x PHY binding
+============================================
+
+This binding describes a miphy device that is used to control PHY hardware
+for SATA and PCIe.
+
+Required properties:
+- compatible: Should be "st,miphy365x-phy"
+- #phy-cells: Should be 2 (See example)
+- reg:	      Address and length of the register set for the device
+- reg-names:  The names of the register addresses corresponding to the
+	      registers filled in "reg".
+- st,syscfg : Should be a phandle of the syscfg node.
+
+Example:
+
+	miphy365x_phy: miphy365x at 0 {
+		compatible = "st,miphy365x-phy";
+		#phy-cells = <1>;
+		reg =	<0xfe382000 0x100>,
+			<0xfe38a000 0x100>,
+			<0xfe394000 0x100>,
+			<0xfe804000 0x100>;
+		reg-names = "sata0", "sata1", "pcie0", "pcie1";
+		st,syscfg= <&syscfg_rear>;
+	};
+
+Specifying phy control of devices
+=================================
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the miphy device node, a port number
+and a device type.
+
+Example:
+
+#include <dt-bindings/phy/phy-miphy365x.h>
+
+	sata0: sata at fe380000 {
+		...
+		phys	  = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
+		...
+	};
-- 
1.8.3.2

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Lee Jones]

This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).

Cc: devicetree at vger.kernel.org
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
new file mode 100644
index 0000000..8757c02
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy365x.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics miphy365x.
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+
+/* Supports 16 ports without a datatype change (u8 & 0xF0). */
+#define MIPHY_PORT_0			0
+#define MIPHY_PORT_1			1
+#define MIPHY_PORT_2			2
+#define MIPHY_PORT_3			3
+
+/* Supports 16 types without a datatype change (u8 & 0x0F). */
+#define MIPHY_TYPE_SHIFT		4
+#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
+
+#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
+#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
+#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
+#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)
+
+#endif /* _DT_BINDINGS_PHY_MIPHY */
-- 
1.8.3.2

[PATCH 3/4] ARM: DT: STi: Add DT node for MiPHY365x

[Lee Jones]

The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.

Cc: devicetree at vger.kernel.org
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/stih416-b2020-revE.dts |  6 +++++-
 arch/arm/boot/dts/stih416-b2020.dts      |  6 ++++++
 arch/arm/boot/dts/stih416.dtsi           | 13 +++++++++++++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts
index a874570..dbe67fa 100644
--- a/arch/arm/boot/dts/stih416-b2020-revE.dts
+++ b/arch/arm/boot/dts/stih416-b2020-revE.dts
@@ -32,6 +32,10 @@
 		ethernet1: ethernet at fef08000 {
 			snps,reset-gpio 	= <&PIO0 7>;
 		};
-	};
 
+		miphy365x_phy: miphy365x at 0 {
+			st,pcie_tx_pol_inv = <1>;
+			st,sata_gen = "gen3";
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 276f28d..fd9cbad 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -13,4 +13,10 @@
 	model = "STiH416 B2020";
 	compatible = "st,stih416", "st,stih416-b2020";
 
+	soc {
+		miphy365x_phy: miphy365x at 0 {
+			st,pcie_tx_pol_inv = <1>;
+			st,sata_gen = "gen3";
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 85b8063..9fd8efb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
 #include "stih41x.dtsi"
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
+
+#include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
 / {
@@ -140,5 +142,16 @@
 			clocks		= <&CLK_S_ICN_REG_0>;
 		};
 
+		miphy365x_phy: miphy365x at 0 {
+			compatible      = "st,miphy365x-phy";
+			reg        	= <0xfe382000 0x100>,
+					  <0xfe38a000 0x100>,
+					  <0xfe394000 0x100>,
+					  <0xfe804000 0x100>;
+			reg-names  	= "sata0", "sata1", "pcie0", "pcie1";
+
+			#phy-cells 	= <2>;
+			st,syscfg  	= <&syscfg_rear>;
+		};
 	};
 };
-- 
1.8.3.2

[PATCH 4/4] phy: miphy365x: Provide support for the MiPHY356x Generic PHY

[Lee Jones]

The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/phy/Kconfig         |   8 +
 drivers/phy/Makefile        |   1 +
 drivers/phy/phy-miphy365x.c | 634 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 643 insertions(+)
 create mode 100644 drivers/phy/phy-miphy365x.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 330ef2d..bb2706a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -21,6 +21,14 @@ config PHY_EXYNOS_MIPI_VIDEO
 	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
 	  and EXYNOS SoCs.
 
+config PHY_MIPHY365X
+	tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series"
+	depends on ARCH_STI
+	depends on GENERIC_PHY
+	help
+	  Enable this to support the miphy transceiver (for SATA/PCIE)
+	  that is part of STMicroelectronics STiH41x SoC series.
+
 config OMAP_USB2
 	tristate "OMAP USB2 PHY Driver"
 	depends on ARCH_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..5879639 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,5 +5,6 @@
 obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_MIPHY365X)		+= phy-miphy365x.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
new file mode 100644
index 0000000..c4124e3
--- /dev/null
+++ b/drivers/phy/phy-miphy365x.c
@@ -0,0 +1,634 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics
+ *
+ * STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
+ *
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy-miphy365x.h>
+
+#define HFC_TIMEOUT		50
+
+#define SYSCFG_2521		0x824
+#define SYSCFG_2522		0x828
+#define SYSCFG_PCIE_SATA_MASK	BIT(1)
+#define SYSCFG_PCIE_SATA_POS	1
+
+/* MiPHY365x register definitiona */
+#define RESET_REG		0x00
+#define RST_PLL			BIT(1)
+#define RST_PLL_CAL		BIT(2)
+#define RST_RX			BIT(4)
+#define RST_MACRO		BIT(7)
+
+#define STATUS_REG		0x01
+#define IDLL_RDY		BIT(0)
+#define PLL_RDY			BIT(1)
+#define DES_BIT_LOCK		BIT(2)
+#define DES_SYMBOL_LOCK		BIT(3)
+
+#define CTRL_REG		0x02
+#define TERM_EN			BIT(0)
+#define PCI_EN			BIT(2)
+#define DES_BIT_LOCK_EN		BIT(3)
+#define TX_POL			BIT(5)
+
+#define INT_CTRL_REG		0x03
+
+#define BOUNDARY1_REG		0x10
+#define SPDSEL_SEL		BIT(0)
+
+#define BOUNDARY3_REG		0x12
+#define TX_SPDSEL_GEN1_VAL	0
+#define TX_SPDSEL_GEN2_VAL	0x01
+#define TX_SPDSEL_GEN3_VAL	0x02
+#define RX_SPDSEL_GEN1_VAL	0
+#define RX_SPDSEL_GEN2_VAL	(0x01 << 3)
+#define RX_SPDSEL_GEN3_VAL	(0x02 << 3)
+
+#define PCIE_REG		0x16
+
+#define BUF_SEL_REG		0x20
+#define CONF_GEN_SEL_GEN3	0x02
+#define CONF_GEN_SEL_GEN2	0x01
+#define PD_VDDTFILTER		BIT(4)
+
+#define TXBUF1_REG		0x21
+#define SWING_VAL		0x04
+#define SWING_VAL_GEN1		0x03
+#define PREEMPH_VAL		(0x3 << 5)
+
+#define TXBUF2_REG		0x22
+#define TXSLEW_VAL		0x2
+#define TXSLEW_VAL_GEN1		0x4
+
+#define RXBUF_OFFSET_CTRL_REG	0x23
+
+#define RXBUF_REG		0x25
+#define SDTHRES_VAL		0x01
+#define EQ_ON3			(0x03 << 4)
+#define EQ_ON1			(0x01 << 4)
+
+#define COMP_CTRL1_REG		0x40
+#define START_COMSR		BIT(0)
+#define START_COMZC		BIT(1)
+#define COMP_AUTO_LOAD		BIT(4)
+
+#define COMP_CTRL2_REG		0x41
+#define COMP_2MHZ_RAT_GEN1	0x1e
+#define COMP_2MHZ_RAT		0xf
+
+#define COMP_CTRL3_REG		0x42
+#define COMSR_COMP_REF		0x33
+
+#define COMP_IDLL_REG		0x47
+#define COMZC_IDLL		0x2a
+
+#define PLL_CTRL1_REG		0x50
+#define PLL_START_CAL		BIT(0)
+#define BUF_EN			BIT(2)
+#define SYNCHRO_TX		BIT(3)
+#define SSC_EN			BIT(6)
+#define CONFIG_PLL		BIT(7)
+
+#define PLL_CTRL2_REG		0x51
+#define BYPASS_PLL_CAL		BIT(1)
+
+#define PLL_RAT_REG		0x52
+
+#define PLL_SSC_STEP_MSB_REG	0x56
+#define PLL_SSC_STEP_MSB_VAL	0x03
+
+#define PLL_SSC_STEP_LSB_REG	0x57
+#define PLL_SSC_STEP_LSB_VAL	0x63
+
+#define PLL_SSC_PER_MSB_REG	0x58
+#define PLL_SSC_PER_MSB_VAL	0
+
+#define PLL_SSC_PER_LSB_REG	0x59
+#define PLL_SSC_PER_LSB_VAL	0xf1
+
+#define IDLL_TEST_REG		0x72
+#define START_CLK_HF		BIT(6)
+
+#define DES_BITLOCK_REG		0x86
+#define BIT_LOCK_LEVEL		0x01
+#define BIT_LOCK_CNT_512	(0x03 << 5)
+
+static u8 ports[] = { MIPHY_PORT_0, MIPHY_PORT_1 };
+
+struct miphy365x_phy {
+	struct phy *phy;
+	void __iomem *base;
+	void __iomem *sata;
+	void __iomem *pcie;
+	u8 type;
+	u8 port;
+};
+
+struct miphy365x_dev {
+	struct device *dev;
+	struct mutex miphy_mutex;
+	struct miphy365x_phy phys[ARRAY_SIZE(ports)];
+	bool pcie_tx_pol_inv;
+	bool sata_tx_pol_inv;
+	u32 sata_gen;
+	struct regmap *regmap;
+};
+
+enum miphy_sata_gen {
+	SATA_GEN1,
+	SATA_GEN2,
+	SATA_GEN3
+};
+
+static u8 rx_tx_spd[] = {
+	TX_SPDSEL_GEN1_VAL | RX_SPDSEL_GEN1_VAL,
+	TX_SPDSEL_GEN2_VAL | RX_SPDSEL_GEN2_VAL,
+	TX_SPDSEL_GEN3_VAL | RX_SPDSEL_GEN3_VAL
+};
+
+#define miphy365x_phy_to_dev(inst) \
+	container_of((inst), struct miphy365x_dev, phys[(inst)->port]);
+
+/*
+ * This function selects the system configuration,
+ * either two SATA, one SATA and one PCIe, or two PCIe lanes.
+ */
+static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
+			      struct miphy365x_dev *miphy_dev)
+{
+	u8 config = miphy_phy->type | miphy_phy->port;
+	u32 mask  = SYSCFG_PCIE_SATA_MASK;
+	u32 reg;
+	bool sata;
+
+	switch (config) {
+	case MIPHY_SATA_PORT0:
+		reg = SYSCFG_2521;
+		sata = true;
+		break;
+	case MIPHY_PCIE_PORT1:
+		reg = SYSCFG_2522;
+		sata = false;
+		break;
+	default:
+		dev_err(miphy_dev->dev, "Configuration not supported\n");
+		return -EINVAL;
+	}
+
+	return regmap_update_bits(miphy_dev->regmap, reg, mask,
+				  sata << SYSCFG_PCIE_SATA_POS);
+}
+
+static void miphy365x_phy_init_pcie_port(struct miphy365x_phy *miphy_phy,
+					 struct miphy365x_dev *miphy_dev)
+{
+	u8 val;
+
+	if (!miphy_dev->pcie_tx_pol_inv)
+		return;
+
+	/* Invert Tx polarity and clear pci_txdetect_pol bit */
+	val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL;
+	writeb_relaxed(val, miphy_phy->base + CTRL_REG);
+	writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
+}
+
+static inline int miphy365x_phy_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
+					    struct miphy365x_dev *miphy_dev)
+{
+	int timeout = HFC_TIMEOUT;
+	u8 mask = IDLL_RDY | PLL_RDY;
+	u8 regval;
+
+	do {
+		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
+		usleep_range(2000, 2500);
+	} while (timeout-- && (regval & mask));
+
+	if (timeout < 0) {
+		dev_err(miphy_dev->dev, "HFC ready timeout!\n");
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static inline int miphy365x_phy_rdy(struct miphy365x_phy *miphy_phy,
+				    struct miphy365x_dev *miphy_dev)
+{
+	int timeout = HFC_TIMEOUT;
+	u8 mask = mask = IDLL_RDY | PLL_RDY;
+	u8 regval;
+
+	do {
+		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
+		usleep_range(2000, 2500);
+	} while (timeout-- && ((regval & mask) != mask));
+
+	if (timeout < 0) {
+		dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static inline void miphy365x_phy_set_comp(struct miphy365x_phy *miphy_phy,
+					  struct miphy365x_dev *miphy_dev)
+{
+	u8 val, mask;
+
+	if (miphy_dev->sata_gen == SATA_GEN1)
+		writeb_relaxed(COMP_2MHZ_RAT_GEN1,
+			       miphy_phy->base + COMP_CTRL2_REG);
+	else
+		writeb_relaxed(COMP_2MHZ_RAT,
+			       miphy_phy->base + COMP_CTRL2_REG);
+
+	if (miphy_dev->sata_gen != SATA_GEN3) {
+		writeb_relaxed(COMSR_COMP_REF,
+			       miphy_phy->base + COMP_CTRL3_REG);
+		/*
+		 * Force VCO current to value defined by address 0x5A
+		 * and disable PCIe100Mref bit
+		 * Enable auto load compensation for pll_i_bias
+		 */
+		writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
+		writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
+	}
+
+	/*
+	 * Force restart compensation and enable auto load
+	 * for Comzc_Tx, Comzc_Rx and Comsr on macro
+	 */
+	val = START_COMSR | START_COMZC | COMP_AUTO_LOAD;
+	writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);
+
+	mask = DES_BIT_LOCK | DES_SYMBOL_LOCK;
+	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask)	!= mask)
+		cpu_relax();
+}
+
+static inline void miphy365x_phy_set_ssc(struct miphy365x_phy *miphy_phy,
+					 struct miphy365x_dev *miphy_dev)
+{
+	u8 val;
+
+	/*
+	 * SSC Settings. SSC will be enabled through Link
+	 * SSC Ampl. = 0.4%
+	 * SSC Freq = 31KHz
+	 */
+	writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
+			miphy_phy->base + PLL_SSC_STEP_MSB_REG);
+	writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
+			miphy_phy->base + PLL_SSC_STEP_LSB_REG);
+	writeb_relaxed(PLL_SSC_PER_MSB_VAL,
+			miphy_phy->base + PLL_SSC_PER_MSB_REG);
+	writeb_relaxed(PLL_SSC_PER_LSB_VAL,
+			miphy_phy->base + PLL_SSC_PER_LSB_REG);
+
+	/* SSC Settings complete */
+	if (miphy_dev->sata_gen == SATA_GEN1) {
+		val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
+		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
+	} else {
+		val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
+		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
+	}
+}
+
+static int miphy365x_phy_init_sata_port(struct miphy365x_phy *miphy_phy,
+					struct miphy365x_dev *miphy_dev)
+{
+	int ret;
+	u8 val;
+
+	/*
+	 * Force PHY macro reset, PLL calibration reset, PLL reset
+	 * and assert Deserializer Reset
+	 */
+	val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
+	writeb_relaxed(val, miphy_phy->base + RESET_REG);
+
+	if (miphy_dev->sata_tx_pol_inv)
+		writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
+
+	/*
+	 * Force macro1 to use rx_lspd, tx_lspd
+	 * Force Rx_Clock on first I-DLL phase
+	 * Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
+	 */
+	writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
+	writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
+	val = rx_tx_spd[miphy_dev->sata_gen];
+	writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
+
+	/* Wait for HFC_READY = 0 */
+	ret = miphy365x_phy_hfc_not_rdy(miphy_phy, miphy_dev);
+	if (ret)
+		return ret;
+
+	/* Compensation Recalibration */
+	miphy365x_phy_set_comp(miphy_phy, miphy_dev);
+
+	switch (miphy_dev->sata_gen) {
+	case SATA_GEN3:
+		/*
+		 * TX Swing target 550-600mv peak to peak diff
+		 * Tx Slew target 90-110ps rising/falling time
+		 * Rx Eq ON3, Sigdet threshold SDTH1
+		 */
+		val = PD_VDDTFILTER | CONF_GEN_SEL_GEN3;
+		writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
+		val = SWING_VAL | PREEMPH_VAL;
+		writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
+		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
+		writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
+		val = SDTHRES_VAL | EQ_ON3;
+		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
+		break;
+	case SATA_GEN2:
+		/*
+		 * conf gen sel=0x1 to program Gen2 banked registers
+		 * VDDT filter ON
+		 * Tx Swing target 550-600mV peak-to-peak diff
+		 * Tx Slew target 90-110 ps rising/falling time
+		 * RX Equalization ON1, Sigdet threshold SDTH1
+		 */
+		writeb_relaxed(CONF_GEN_SEL_GEN2,
+			       miphy_phy->base + BUF_SEL_REG);
+		writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
+		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
+		val = SDTHRES_VAL | EQ_ON1;
+		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
+		break;
+	case SATA_GEN1:
+		/*
+		 * conf gen sel = 00b to program Gen1 banked registers
+		 * VDDT filter ON
+		 * Tx Swing target 500-550mV peak-to-peak diff
+		 * Tx Slew target120-140 ps rising/falling time
+		 */
+		writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
+		writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
+		writeb_relaxed(TXSLEW_VAL_GEN1,	miphy_phy->base + TXBUF2_REG);
+		break;
+	default:
+		break;
+	}
+
+	/* Force Macro1 in partial mode & release pll cal reset */
+	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
+	usleep_range(100, 150);
+
+	miphy365x_phy_set_ssc(miphy_phy, miphy_dev);
+
+	/* Wait for phy_ready */
+	ret = miphy365x_phy_rdy(miphy_phy, miphy_dev);
+	if (ret)
+		return ret;
+
+	/*
+	 * Enable macro1 to use rx_lspd & tx_lspd
+	 * Release Rx_Clock on first I-DLL phase on macro1
+	 * Assert deserializer reset
+	 * des_bit_lock_en is set
+	 * bit lock detection strength
+	 * Deassert deserializer reset
+	 */
+	writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
+	writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
+	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
+	val = miphy_dev->sata_tx_pol_inv ?
+		(TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
+	writeb_relaxed(val, miphy_phy->base + CTRL_REG);
+
+	val = BIT_LOCK_CNT_512 | BIT_LOCK_LEVEL;
+	writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
+	writeb_relaxed(0x00, miphy_phy->base + RESET_REG);
+
+	return 0;
+}
+
+static int miphy365x_phy_init(struct phy *phy)
+{
+	int ret = 0;
+	struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
+	struct miphy365x_dev *miphy_dev = miphy365x_phy_to_dev(miphy_phy);
+
+	mutex_lock(&miphy_dev->miphy_mutex);
+
+	ret = miphy365x_set_path(miphy_phy, miphy_dev);
+	if (ret) {
+		mutex_unlock(&miphy_dev->miphy_mutex);
+		return ret;
+	}
+
+	/* Initialise Miphy for PCIe or SATA */
+	if (miphy_phy->type == MIPHY_TYPE_PCIE)
+		miphy365x_phy_init_pcie_port(miphy_phy, miphy_dev);
+	else
+		ret = miphy365x_phy_init_sata_port(miphy_phy, miphy_dev);
+
+	mutex_unlock(&miphy_dev->miphy_mutex);
+
+	return ret;
+}
+
+static int miphy365x_phy_power_on(struct phy *phy)
+{
+	return 0;
+}
+
+static int miphy365x_phy_power_off(struct phy *phy)
+{
+	return 0;
+}
+
+static struct phy *miphy365x_phy_xlate(struct device *dev,
+				       struct of_phandle_args *args)
+{
+	struct miphy365x_dev *state = dev_get_drvdata(dev);
+	u8 port = args->args[0];
+	u8 type = args->args[1];
+
+	if (WARN_ON(port >= ARRAY_SIZE(ports)))
+		return ERR_PTR(-EINVAL);
+
+	if (type == MIPHY_TYPE_SATA)
+		state->phys[port].base = state->phys[port].sata;
+	else if (type == MIPHY_TYPE_PCIE)
+		state->phys[port].base = state->phys[port].pcie;
+	else {
+		WARN(1, "Invalid type specified in DT");
+		return ERR_PTR(-EINVAL);
+	}
+
+	state->phys[port].type = type;
+
+	return state->phys[port].phy;
+}
+
+static struct phy_ops miphy365x_phy_ops = {
+	.init		= miphy365x_phy_init,
+	.power_on	= miphy365x_phy_power_on,
+	.power_off	= miphy365x_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int miphy365x_phy_get_base_addr(struct platform_device *pdev,
+				       struct miphy365x_phy *phy, u8 port)
+{
+	struct resource *res;
+	char sata[16];
+	char pcie[16];
+
+	sprintf(sata, "sata%d", port);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, sata);
+	if (!res)
+		return -ENODEV;
+
+	phy->sata = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+	if (!phy->sata)
+		return -ENOMEM;
+
+	sprintf(pcie, "pcie%d", port);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pcie);
+	if (!res)
+		return -ENODEV;
+
+	phy->pcie = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+	if (!phy->pcie)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int miphy365x_phy_of_probe(struct device_node *np,
+				  struct miphy365x_dev *phy_dev)
+{
+	const char *sata_gen;
+
+	phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+	if (IS_ERR(phy_dev->regmap)) {
+		dev_err(phy_dev->dev, "No syscfg phandle specified\n");
+		return PTR_ERR(phy_dev->regmap);
+	}
+
+	/* Default */
+	phy_dev->sata_gen = SATA_GEN1;
+
+	of_property_read_string(np, "st,sata_gen", &sata_gen);
+	if (sata_gen) {
+		if (!strcmp(sata_gen, "gen3"))
+			phy_dev->sata_gen = SATA_GEN3;
+		else if (!strcmp(sata_gen, "gen2"))
+			phy_dev->sata_gen = SATA_GEN2;
+	}
+
+	phy_dev->pcie_tx_pol_inv =
+		of_property_read_bool(np, "st,pcie_tx_pol_inv");
+
+	phy_dev->sata_tx_pol_inv =
+		of_property_read_bool(np, "st,sata_tx_pol_inv");
+
+	return 0;
+}
+
+static int miphy365x_phy_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct miphy365x_dev *phy_dev;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *provider;
+	u8 port;
+	int ret;
+
+	if (!np) {
+		dev_err(dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
+	if (!phy_dev)
+		return -ENOMEM;
+
+	ret = miphy365x_phy_of_probe(np, phy_dev);
+	if (ret)
+		return ret;
+
+	phy_dev->dev = dev;
+
+	dev_set_drvdata(dev, phy_dev);
+
+	mutex_init(&phy_dev->miphy_mutex);
+
+	provider = devm_of_phy_provider_register(dev, miphy365x_phy_xlate);
+	if (IS_ERR(provider))
+		return PTR_ERR(provider);
+
+	for (port = 0; port < ARRAY_SIZE(ports); port++) {
+		struct phy *phy;
+
+		phy = devm_phy_create(dev, &miphy365x_phy_ops, NULL);
+		if (IS_ERR(phy)) {
+			dev_err(dev, "failed to create PHY on port %d\n", port);
+			return PTR_ERR(phy);
+		}
+
+		phy_dev->phys[port].phy  = phy;
+		phy_dev->phys[port].port = port;
+
+		ret = miphy365x_phy_get_base_addr(pdev,
+					&phy_dev->phys[port], port);
+		if (ret)
+			return ret;
+
+		phy_set_drvdata(phy, &phy_dev->phys[port]);
+	}
+
+	return 0;
+}
+
+static const struct of_device_id miphy365x_phy_of_match[] = {
+	{ .compatible = "st,miphy365x-phy", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, miphy365x_phy_of_match);
+
+static struct platform_driver miphy365x_phy_driver = {
+	.probe	= miphy365x_phy_probe,
+	.driver = {
+		.name	= "miphy365x-phy",
+		.owner	= THIS_MODULE,
+		.of_match_table	= miphy365x_phy_of_match,
+	}
+};
+module_platform_driver(miphy365x_phy_driver);
+
+MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics miphy365x driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.3.2

[PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x

[Mark Rutland]

On Wed, Feb 12, 2014 at 04:03:02PM +0000, Lee Jones wrote:
> The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> devices. It has 2 ports which it can use for either; both SATA, both
> PCIe or one of each in any configuration.
> 
> Cc: devicetree at vger.kernel.org
> Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 43 ++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> new file mode 100644
> index 0000000..fdfa7ca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> @@ -0,0 +1,43 @@
> +STMicroelectronics STi MIPHY365x PHY binding
> +============================================
> +
> +This binding describes a miphy device that is used to control PHY hardware
> +for SATA and PCIe.
> +
> +Required properties:
> +- compatible: Should be "st,miphy365x-phy"
> +- #phy-cells: Should be 2 (See example)

The first example has #phy-cells = <1>.

What do the cells mean? What are the expected values?

> +- reg:	      Address and length of the register set for the device
> +- reg-names:  The names of the register addresses corresponding to the
> +	      registers filled in "reg".

Whenever there is a ${PROP}-names property, there should be a list of
explicit values, and a description of how it relates to ${PROP}. Without
that it's a bit useless.

Please provide an explicit list of expected names here.

I assume here what you want is something like:

- reg: a list of address + length pairs, one for each entry in reg-names
- reg-names: should contain:
  * "sata0" for the sata0 control registers...
  * "sata1" ...
  * "pcie0" ...
  * "pcie1" ...

> +- st,syscfg : Should be a phandle of the syscfg node.

What's this used for?

Cheers,
Mark.

[PATCH 4/4] phy: miphy365x: Provide support for the MiPHY356x Generic PHY

[Mark Rutland]

On Wed, Feb 12, 2014 at 04:03:05PM +0000, Lee Jones wrote:
> The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> devices. It has 2 ports which it can use for either; both SATA, both
> PCIe or one of each in any configuration.
>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
>  drivers/phy/Kconfig         |   8 +
>  drivers/phy/Makefile        |   1 +
>  drivers/phy/phy-miphy365x.c | 634 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 643 insertions(+)
>  create mode 100644 drivers/phy/phy-miphy365x.c
>

[...]

> +static int miphy365x_phy_get_base_addr(struct platform_device *pdev,
> +                                      struct miphy365x_phy *phy, u8 port)
> +{
> +       struct resource *res;
> +       char sata[16];
> +       char pcie[16];

Isn't 6 enough for either of these? There are at most two ports IIUC, so
we only need a single character for the port number.

> +
> +       sprintf(sata, "sata%d", port);
> +
> +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, sata);
> +       if (!res)
> +               return -ENODEV;
> +
> +       phy->sata = devm_ioremap(&pdev->dev, res->start, resource_size(res));
> +       if (!phy->sata)
> +               return -ENOMEM;
> +
> +       sprintf(pcie, "pcie%d", port);
> +
> +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pcie);
> +       if (!res)
> +               return -ENODEV;
> +
> +       phy->pcie = devm_ioremap(&pdev->dev, res->start, resource_size(res));
> +       if (!phy->pcie)
> +               return -ENOMEM;
> +
> +       return 0;
> +}
> +
> +static int miphy365x_phy_of_probe(struct device_node *np,
> +                                 struct miphy365x_dev *phy_dev)
> +{
> +       const char *sata_gen;
> +
> +       phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
> +       if (IS_ERR(phy_dev->regmap)) {
> +               dev_err(phy_dev->dev, "No syscfg phandle specified\n");
> +               return PTR_ERR(phy_dev->regmap);
> +       }
> +
> +       /* Default */
> +       phy_dev->sata_gen = SATA_GEN1;
> +
> +       of_property_read_string(np, "st,sata_gen", &sata_gen);

This wasn't in the binding documentation. It also violates dt style;
s/_/-/

Could these not be numbers, or can this not come from elsewhere?

Or are there some crazy SATA generations to support?

> +       if (sata_gen) {
> +               if (!strcmp(sata_gen, "gen3"))
> +                       phy_dev->sata_gen = SATA_GEN3;
> +               else if (!strcmp(sata_gen, "gen2"))
> +                       phy_dev->sata_gen = SATA_GEN2;
> +       }
> +
> +       phy_dev->pcie_tx_pol_inv =
> +               of_property_read_bool(np, "st,pcie_tx_pol_inv");
> +
> +       phy_dev->sata_tx_pol_inv =
> +               of_property_read_bool(np, "st,sata_tx_pol_inv");

Likewise for both of these on the first two points.

> +
> +       return 0;
> +}
> +
> +static int miphy365x_phy_probe(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct miphy365x_dev *phy_dev;
> +       struct device *dev = &pdev->dev;
> +       struct phy_provider *provider;
> +       u8 port;
> +       int ret;
> +
> +       if (!np) {
> +               dev_err(dev, "No DT found\n");

s/DT/node/ ?

Cheers,
Mark.

[PATCH 4/4] phy: miphy365x: Provide support for the MiPHY356x Generic PHY

[Kishon Vijay Abraham I]

Hi,

On Wednesday 12 February 2014 09:33 PM, Lee Jones wrote:
> The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> devices. It has 2 ports which it can use for either; both SATA, both

various SATA or PCIe devices in STMicroelectronics STiH41x SoC series?
> PCIe or one of each in any configuration.
> 
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
>  drivers/phy/Kconfig         |   8 +
>  drivers/phy/Makefile        |   1 +
>  drivers/phy/phy-miphy365x.c | 634 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 643 insertions(+)
>  create mode 100644 drivers/phy/phy-miphy365x.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 330ef2d..bb2706a 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -21,6 +21,14 @@ config PHY_EXYNOS_MIPI_VIDEO
>  	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
>  	  and EXYNOS SoCs.
>  
> +config PHY_MIPHY365X
> +	tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series"
> +	depends on ARCH_STI
> +	depends on GENERIC_PHY
depends on CONFIG_OF and HAS_IOMEM?
> +	help
> +	  Enable this to support the miphy transceiver (for SATA/PCIE)
> +	  that is part of STMicroelectronics STiH41x SoC series.
> +
>  config OMAP_USB2
>  	tristate "OMAP USB2 PHY Driver"
>  	depends on ARCH_OMAP2PLUS
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d0caae9..5879639 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -5,5 +5,6 @@
>  obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
>  obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
>  obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> +obj-$(CONFIG_PHY_MIPHY365X)		+= phy-miphy365x.o
>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
> new file mode 100644
> index 0000000..c4124e3
> --- /dev/null
> +++ b/drivers/phy/phy-miphy365x.c
> @@ -0,0 +1,634 @@
> +/*
> + * Copyright (C) 2014 STMicroelectronics
> + *
> + * STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
> + *
> + * Author: Alexandre Torgue <alexandre.torgue@st.com>

The author of this patch is not Alexandre Torgue?
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2, as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/phy/phy-miphy365x.h>
> +
> +#define HFC_TIMEOUT		50
> +
> +#define SYSCFG_2521		0x824
> +#define SYSCFG_2522		0x828
> +#define SYSCFG_PCIE_SATA_MASK	BIT(1)
> +#define SYSCFG_PCIE_SATA_POS	1
> +
> +/* MiPHY365x register definitiona */
> +#define RESET_REG		0x00
> +#define RST_PLL			BIT(1)

There are quite a few alignment problems with these macros. It needs to be fixed.
> +#define RST_PLL_CAL		BIT(2)
> +#define RST_RX			BIT(4)
> +#define RST_MACRO		BIT(7)
> +
> +#define STATUS_REG		0x01
> +#define IDLL_RDY		BIT(0)
> +#define PLL_RDY			BIT(1)
> +#define DES_BIT_LOCK		BIT(2)
> +#define DES_SYMBOL_LOCK		BIT(3)
> +
> +#define CTRL_REG		0x02
> +#define TERM_EN			BIT(0)
> +#define PCI_EN			BIT(2)
> +#define DES_BIT_LOCK_EN		BIT(3)
> +#define TX_POL			BIT(5)
> +
> +#define INT_CTRL_REG		0x03
> +
> +#define BOUNDARY1_REG		0x10
> +#define SPDSEL_SEL		BIT(0)
> +
> +#define BOUNDARY3_REG		0x12
> +#define TX_SPDSEL_GEN1_VAL	0
> +#define TX_SPDSEL_GEN2_VAL	0x01
> +#define TX_SPDSEL_GEN3_VAL	0x02
> +#define RX_SPDSEL_GEN1_VAL	0
> +#define RX_SPDSEL_GEN2_VAL	(0x01 << 3)
> +#define RX_SPDSEL_GEN3_VAL	(0x02 << 3)
> +
> +#define PCIE_REG		0x16
> +
> +#define BUF_SEL_REG		0x20
> +#define CONF_GEN_SEL_GEN3	0x02
> +#define CONF_GEN_SEL_GEN2	0x01
> +#define PD_VDDTFILTER		BIT(4)
> +
> +#define TXBUF1_REG		0x21
> +#define SWING_VAL		0x04
> +#define SWING_VAL_GEN1		0x03
> +#define PREEMPH_VAL		(0x3 << 5)
> +
> +#define TXBUF2_REG		0x22
> +#define TXSLEW_VAL		0x2
> +#define TXSLEW_VAL_GEN1		0x4
> +
> +#define RXBUF_OFFSET_CTRL_REG	0x23
> +
> +#define RXBUF_REG		0x25
> +#define SDTHRES_VAL		0x01
> +#define EQ_ON3			(0x03 << 4)
> +#define EQ_ON1			(0x01 << 4)
> +
> +#define COMP_CTRL1_REG		0x40
> +#define START_COMSR		BIT(0)
> +#define START_COMZC		BIT(1)
> +#define COMP_AUTO_LOAD		BIT(4)
> +
> +#define COMP_CTRL2_REG		0x41
> +#define COMP_2MHZ_RAT_GEN1	0x1e
> +#define COMP_2MHZ_RAT		0xf
> +
> +#define COMP_CTRL3_REG		0x42
> +#define COMSR_COMP_REF		0x33
> +
> +#define COMP_IDLL_REG		0x47
> +#define COMZC_IDLL		0x2a
> +
> +#define PLL_CTRL1_REG		0x50
> +#define PLL_START_CAL		BIT(0)
> +#define BUF_EN			BIT(2)
> +#define SYNCHRO_TX		BIT(3)
> +#define SSC_EN			BIT(6)
> +#define CONFIG_PLL		BIT(7)
> +
> +#define PLL_CTRL2_REG		0x51
> +#define BYPASS_PLL_CAL		BIT(1)
> +
> +#define PLL_RAT_REG		0x52
> +
> +#define PLL_SSC_STEP_MSB_REG	0x56
> +#define PLL_SSC_STEP_MSB_VAL	0x03
> +
> +#define PLL_SSC_STEP_LSB_REG	0x57
> +#define PLL_SSC_STEP_LSB_VAL	0x63
> +
> +#define PLL_SSC_PER_MSB_REG	0x58
> +#define PLL_SSC_PER_MSB_VAL	0
> +
> +#define PLL_SSC_PER_LSB_REG	0x59
> +#define PLL_SSC_PER_LSB_VAL	0xf1
> +
> +#define IDLL_TEST_REG		0x72
> +#define START_CLK_HF		BIT(6)
> +
> +#define DES_BITLOCK_REG		0x86
> +#define BIT_LOCK_LEVEL		0x01
> +#define BIT_LOCK_CNT_512	(0x03 << 5)
> +
> +static u8 ports[] = { MIPHY_PORT_0, MIPHY_PORT_1 };
> +
> +struct miphy365x_phy {
> +	struct phy *phy;
> +	void __iomem *base;
> +	void __iomem *sata;
> +	void __iomem *pcie;
> +	u8 type;
> +	u8 port;
> +};
> +
> +struct miphy365x_dev {
> +	struct device *dev;
> +	struct mutex miphy_mutex;
> +	struct miphy365x_phy phys[ARRAY_SIZE(ports)];
> +	bool pcie_tx_pol_inv;
> +	bool sata_tx_pol_inv;
> +	u32 sata_gen;
> +	struct regmap *regmap;
> +};
> +
> +enum miphy_sata_gen {
> +	SATA_GEN1,
> +	SATA_GEN2,
> +	SATA_GEN3
> +};
> +
> +static u8 rx_tx_spd[] = {
> +	TX_SPDSEL_GEN1_VAL | RX_SPDSEL_GEN1_VAL,
> +	TX_SPDSEL_GEN2_VAL | RX_SPDSEL_GEN2_VAL,
> +	TX_SPDSEL_GEN3_VAL | RX_SPDSEL_GEN3_VAL
> +};
> +
> +#define miphy365x_phy_to_dev(inst) \
> +	container_of((inst), struct miphy365x_dev, phys[(inst)->port]);
> +
> +/*
> + * This function selects the system configuration,
> + * either two SATA, one SATA and one PCIe, or two PCIe lanes.
> + */
> +static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
> +			      struct miphy365x_dev *miphy_dev)
> +{
> +	u8 config = miphy_phy->type | miphy_phy->port;
> +	u32 mask  = SYSCFG_PCIE_SATA_MASK;
> +	u32 reg;
> +	bool sata;
> +
> +	switch (config) {
> +	case MIPHY_SATA_PORT0:
> +		reg = SYSCFG_2521;
> +		sata = true;

How do we configure PORT1 for SATA here? Do we really support all the system
configuration?
> +		break;
> +	case MIPHY_PCIE_PORT1:
> +		reg = SYSCFG_2522;
> +		sata = false;
> +		break;
> +	default:
> +		dev_err(miphy_dev->dev, "Configuration not supported\n");
> +		return -EINVAL;
> +	}
> +
> +	return regmap_update_bits(miphy_dev->regmap, reg, mask,
> +				  sata << SYSCFG_PCIE_SATA_POS);
> +}
> +
> +static void miphy365x_phy_init_pcie_port(struct miphy365x_phy *miphy_phy,
> +					 struct miphy365x_dev *miphy_dev)
> +{
> +	u8 val;
> +
> +	if (!miphy_dev->pcie_tx_pol_inv)
> +		return;
> +
> +	/* Invert Tx polarity and clear pci_txdetect_pol bit */
> +	val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL;
> +	writeb_relaxed(val, miphy_phy->base + CTRL_REG);
> +	writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
> +}
> +
> +static inline int miphy365x_phy_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
> +					    struct miphy365x_dev *miphy_dev)
> +{
> +	int timeout = HFC_TIMEOUT;
> +	u8 mask = IDLL_RDY | PLL_RDY;
> +	u8 regval;
> +
> +	do {
> +		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
> +		usleep_range(2000, 2500);

Any comment on how this delay value is obtained?
> +	} while (timeout-- && (regval & mask));
> +
> +	if (timeout < 0) {
> +		dev_err(miphy_dev->dev, "HFC ready timeout!\n");
> +		return -EBUSY;
> +	}
> +
> +	return 0;
> +}
> +
> +static inline int miphy365x_phy_rdy(struct miphy365x_phy *miphy_phy,
> +				    struct miphy365x_dev *miphy_dev)
> +{
> +	int timeout = HFC_TIMEOUT;
> +	u8 mask = mask = IDLL_RDY | PLL_RDY;

just u8 mask = IDLL_RDY | PLL_RDY; would suffice.
> +	u8 regval;
> +
> +	do {
> +		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
> +		usleep_range(2000, 2500);

same here.
> +	} while (timeout-- && ((regval & mask) != mask));
> +
> +	if (timeout < 0) {
> +		dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
> +		return -EBUSY;
> +	}
> +
> +	return 0;
> +}
> +
> +static inline void miphy365x_phy_set_comp(struct miphy365x_phy *miphy_phy,
> +					  struct miphy365x_dev *miphy_dev)
> +{
> +	u8 val, mask;
> +
> +	if (miphy_dev->sata_gen == SATA_GEN1)
> +		writeb_relaxed(COMP_2MHZ_RAT_GEN1,
> +			       miphy_phy->base + COMP_CTRL2_REG);
> +	else
> +		writeb_relaxed(COMP_2MHZ_RAT,
> +			       miphy_phy->base + COMP_CTRL2_REG);
> +
> +	if (miphy_dev->sata_gen != SATA_GEN3) {
> +		writeb_relaxed(COMSR_COMP_REF,
> +			       miphy_phy->base + COMP_CTRL3_REG);
> +		/*
> +		 * Force VCO current to value defined by address 0x5A
> +		 * and disable PCIe100Mref bit
> +		 * Enable auto load compensation for pll_i_bias
> +		 */
> +		writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
> +		writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
> +	}
> +
> +	/*
> +	 * Force restart compensation and enable auto load
> +	 * for Comzc_Tx, Comzc_Rx and Comsr on macro
> +	 */
> +	val = START_COMSR | START_COMZC | COMP_AUTO_LOAD;
> +	writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);
> +
> +	mask = DES_BIT_LOCK | DES_SYMBOL_LOCK;
> +	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask)	!= mask)
> +		cpu_relax();

Don't we need to break from here at some point if the LOCK's are never set?
> +}
> +
> +static inline void miphy365x_phy_set_ssc(struct miphy365x_phy *miphy_phy,
> +					 struct miphy365x_dev *miphy_dev)
> +{
> +	u8 val;
> +
> +	/*
> +	 * SSC Settings. SSC will be enabled through Link
> +	 * SSC Ampl. = 0.4%
> +	 * SSC Freq = 31KHz
> +	 */
> +	writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
> +			miphy_phy->base + PLL_SSC_STEP_MSB_REG);
> +	writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
> +			miphy_phy->base + PLL_SSC_STEP_LSB_REG);
> +	writeb_relaxed(PLL_SSC_PER_MSB_VAL,
> +			miphy_phy->base + PLL_SSC_PER_MSB_REG);
> +	writeb_relaxed(PLL_SSC_PER_LSB_VAL,
> +			miphy_phy->base + PLL_SSC_PER_LSB_REG);
> +
> +	/* SSC Settings complete */
> +	if (miphy_dev->sata_gen == SATA_GEN1) {
> +		val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
> +		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
> +	} else {
> +		val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
> +		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
> +	}
> +}
> +
> +static int miphy365x_phy_init_sata_port(struct miphy365x_phy *miphy_phy,
> +					struct miphy365x_dev *miphy_dev)
> +{
> +	int ret;
> +	u8 val;
> +
> +	/*
> +	 * Force PHY macro reset, PLL calibration reset, PLL reset
> +	 * and assert Deserializer Reset
> +	 */
> +	val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
> +	writeb_relaxed(val, miphy_phy->base + RESET_REG);
> +
> +	if (miphy_dev->sata_tx_pol_inv)
> +		writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
> +
> +	/*
> +	 * Force macro1 to use rx_lspd, tx_lspd
> +	 * Force Rx_Clock on first I-DLL phase
> +	 * Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
> +	 */
> +	writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
> +	writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
> +	val = rx_tx_spd[miphy_dev->sata_gen];
> +	writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
> +
> +	/* Wait for HFC_READY = 0 */
> +	ret = miphy365x_phy_hfc_not_rdy(miphy_phy, miphy_dev);
> +	if (ret)
> +		return ret;
> +
> +	/* Compensation Recalibration */
> +	miphy365x_phy_set_comp(miphy_phy, miphy_dev);
> +
> +	switch (miphy_dev->sata_gen) {
> +	case SATA_GEN3:
> +		/*
> +		 * TX Swing target 550-600mv peak to peak diff
> +		 * Tx Slew target 90-110ps rising/falling time
> +		 * Rx Eq ON3, Sigdet threshold SDTH1
> +		 */
> +		val = PD_VDDTFILTER | CONF_GEN_SEL_GEN3;
> +		writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
> +		val = SWING_VAL | PREEMPH_VAL;
> +		writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
> +		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
> +		writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
> +		val = SDTHRES_VAL | EQ_ON3;
> +		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
> +		break;
> +	case SATA_GEN2:
> +		/*
> +		 * conf gen sel=0x1 to program Gen2 banked registers
> +		 * VDDT filter ON
> +		 * Tx Swing target 550-600mV peak-to-peak diff
> +		 * Tx Slew target 90-110 ps rising/falling time
> +		 * RX Equalization ON1, Sigdet threshold SDTH1
> +		 */
> +		writeb_relaxed(CONF_GEN_SEL_GEN2,
> +			       miphy_phy->base + BUF_SEL_REG);
> +		writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
> +		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
> +		val = SDTHRES_VAL | EQ_ON1;
> +		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
> +		break;
> +	case SATA_GEN1:
> +		/*
> +		 * conf gen sel = 00b to program Gen1 banked registers
> +		 * VDDT filter ON
> +		 * Tx Swing target 500-550mV peak-to-peak diff
> +		 * Tx Slew target120-140 ps rising/falling time
> +		 */
> +		writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
> +		writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
> +		writeb_relaxed(TXSLEW_VAL_GEN1,	miphy_phy->base + TXBUF2_REG);
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	/* Force Macro1 in partial mode & release pll cal reset */
> +	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
> +	usleep_range(100, 150);
> +
> +	miphy365x_phy_set_ssc(miphy_phy, miphy_dev);
> +
> +	/* Wait for phy_ready */
> +	ret = miphy365x_phy_rdy(miphy_phy, miphy_dev);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Enable macro1 to use rx_lspd & tx_lspd
> +	 * Release Rx_Clock on first I-DLL phase on macro1
> +	 * Assert deserializer reset
> +	 * des_bit_lock_en is set
> +	 * bit lock detection strength
> +	 * Deassert deserializer reset
> +	 */
> +	writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
> +	writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
> +	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
> +	val = miphy_dev->sata_tx_pol_inv ?
> +		(TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
> +	writeb_relaxed(val, miphy_phy->base + CTRL_REG);
> +
> +	val = BIT_LOCK_CNT_512 | BIT_LOCK_LEVEL;
> +	writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
> +	writeb_relaxed(0x00, miphy_phy->base + RESET_REG);
> +
> +	return 0;
> +}
> +
> +static int miphy365x_phy_init(struct phy *phy)
> +{
> +	int ret = 0;
> +	struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
> +	struct miphy365x_dev *miphy_dev = miphy365x_phy_to_dev(miphy_phy);
> +
> +	mutex_lock(&miphy_dev->miphy_mutex);
> +
> +	ret = miphy365x_set_path(miphy_phy, miphy_dev);
> +	if (ret) {
> +		mutex_unlock(&miphy_dev->miphy_mutex);
> +		return ret;
> +	}
> +
> +	/* Initialise Miphy for PCIe or SATA */
> +	if (miphy_phy->type == MIPHY_TYPE_PCIE)
> +		miphy365x_phy_init_pcie_port(miphy_phy, miphy_dev);
> +	else
> +		ret = miphy365x_phy_init_sata_port(miphy_phy, miphy_dev);
> +
> +	mutex_unlock(&miphy_dev->miphy_mutex);
> +
> +	return ret;
> +}
> +
> +static int miphy365x_phy_power_on(struct phy *phy)
> +{
> +	return 0;
> +}
> +
> +static int miphy365x_phy_power_off(struct phy *phy)
> +{
> +	return 0;
> +}

Both these empty functions can be removed.
> +
> +static struct phy *miphy365x_phy_xlate(struct device *dev,
> +				       struct of_phandle_args *args)
> +{
> +	struct miphy365x_dev *state = dev_get_drvdata(dev);
> +	u8 port = args->args[0];
> +	u8 type = args->args[1];
> +
> +	if (WARN_ON(port >= ARRAY_SIZE(ports)))
> +		return ERR_PTR(-EINVAL);
> +
> +	if (type == MIPHY_TYPE_SATA)
> +		state->phys[port].base = state->phys[port].sata;
> +	else if (type == MIPHY_TYPE_PCIE)
> +		state->phys[port].base = state->phys[port].pcie;
> +	else {
> +		WARN(1, "Invalid type specified in DT");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	state->phys[port].type = type;
> +
> +	return state->phys[port].phy;
> +}
> +
> +static struct phy_ops miphy365x_phy_ops = {
> +	.init		= miphy365x_phy_init,
> +	.power_on	= miphy365x_phy_power_on,
> +	.power_off	= miphy365x_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int miphy365x_phy_get_base_addr(struct platform_device *pdev,
> +				       struct miphy365x_phy *phy, u8 port)
> +{
> +	struct resource *res;
> +	char sata[16];
> +	char pcie[16];

It can be done with a single variable ;-)
> +
> +	sprintf(sata, "sata%d", port);
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, sata);
> +	if (!res)
> +		return -ENODEV;
> +
> +	phy->sata = devm_ioremap(&pdev->dev, res->start, resource_size(res));
> +	if (!phy->sata)
> +		return -ENOMEM;
> +
> +	sprintf(pcie, "pcie%d", port);
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pcie);
> +	if (!res)
> +		return -ENODEV;
> +
> +	phy->pcie = devm_ioremap(&pdev->dev, res->start, resource_size(res));
> +	if (!phy->pcie)
> +		return -ENOMEM;
> +
> +	return 0;
> +}
> +
> +static int miphy365x_phy_of_probe(struct device_node *np,
> +				  struct miphy365x_dev *phy_dev)
> +{
> +	const char *sata_gen;
> +
> +	phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
> +	if (IS_ERR(phy_dev->regmap)) {
> +		dev_err(phy_dev->dev, "No syscfg phandle specified\n");
> +		return PTR_ERR(phy_dev->regmap);
> +	}
> +
> +	/* Default */
> +	phy_dev->sata_gen = SATA_GEN1;
> +
> +	of_property_read_string(np, "st,sata_gen", &sata_gen);
> +	if (sata_gen) {
> +		if (!strcmp(sata_gen, "gen3"))
> +			phy_dev->sata_gen = SATA_GEN3;
> +		else if (!strcmp(sata_gen, "gen2"))
> +			phy_dev->sata_gen = SATA_GEN2;
> +	}
> +
> +	phy_dev->pcie_tx_pol_inv =
> +		of_property_read_bool(np, "st,pcie_tx_pol_inv");
> +
> +	phy_dev->sata_tx_pol_inv =
> +		of_property_read_bool(np, "st,sata_tx_pol_inv");
> +
> +	return 0;
> +}
> +
> +static int miphy365x_phy_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct miphy365x_dev *phy_dev;
> +	struct device *dev = &pdev->dev;
> +	struct phy_provider *provider;
> +	u8 port;
> +	int ret;
> +
> +	if (!np) {
> +		dev_err(dev, "No DT found\n");
> +		return -EINVAL;
> +	}
> +
> +	phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
> +	if (!phy_dev)
> +		return -ENOMEM;
> +
> +	ret = miphy365x_phy_of_probe(np, phy_dev);
> +	if (ret)
> +		return ret;
> +
> +	phy_dev->dev = dev;
> +
> +	dev_set_drvdata(dev, phy_dev);
> +
> +	mutex_init(&phy_dev->miphy_mutex);
> +
> +	provider = devm_of_phy_provider_register(dev, miphy365x_phy_xlate);
> +	if (IS_ERR(provider))
> +		return PTR_ERR(provider);

Phy provider register should be the last step in registering the PHY.

Thanks
Kishon

[PATCH 4/4] phy: miphy365x: Provide support for the MiPHY356x Generic PHY

[Lee Jones]

> > The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> > devices. It has 2 ports which it can use for either; both SATA, both
> 
> various SATA or PCIe devices in STMicroelectronics STiH41x SoC series?

To tell you the truth, I'm not sure if it is limited to ST's h/w, but
I think it can only be found there, so I'm happy to fixup.

<snip>

> > +config PHY_MIPHY365X
> > +	tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series"
> > +	depends on ARCH_STI
> > +	depends on GENERIC_PHY
> depends on CONFIG_OF and HAS_IOMEM?

Sure, I'll fix.

<snip>

> > + * Copyright (C) 2014 STMicroelectronics
> > + *
> > + * STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
> > + *
> > + * Author: Alexandre Torgue <alexandre.torgue@st.com>
> 
> The author of this patch is not Alexandre Torgue?

The history of this driver is long and the authors are many. Alex
did the last internal over-haul and converted it to use Generic PHY. I
took Alex's driver and made significant changes in order to upstream.

<snip>

> > +#define HFC_TIMEOUT		50
> > +
> > +#define SYSCFG_2521		0x824
> > +#define SYSCFG_2522		0x828
> > +#define SYSCFG_PCIE_SATA_MASK	BIT(1)
> > +#define SYSCFG_PCIE_SATA_POS	1
> > +
> > +/* MiPHY365x register definitiona */
> > +#define RESET_REG		0x00
> > +#define RST_PLL			BIT(1)
> 
> There are quite a few alignment problems with these macros. It needs
> to be fixed.

This is just Git playing up.

In reality everything is perfectly aligned and all using tabs.

<snip>

> > +/*
> > + * This function selects the system configuration,
> > + * either two SATA, one SATA and one PCIe, or two PCIe lanes.
> > + */
> > +static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
> > +			      struct miphy365x_dev *miphy_dev)
> > +{
> > +	u8 config = miphy_phy->type | miphy_phy->port;
> > +	u32 mask  = SYSCFG_PCIE_SATA_MASK;
> > +	u32 reg;
> > +	bool sata;
> > +
> > +	switch (config) {
> > +	case MIPHY_SATA_PORT0:
> > +		reg = SYSCFG_2521;
> > +		sata = true;
> 
> How do we configure PORT1 for SATA here? Do we really support all the system
> configuration?

Good spot eagle-eye!

Actually in the current version there is a h/w bug which only allows
the SATA_PORT0 and PCIE_PORT1 configuration. When a new version fixing
this is released I will add version detection to the driver and we can
support full intended configuration options. 

<snip>

> > +static inline int miphy365x_phy_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
> > +					    struct miphy365x_dev *miphy_dev)
> > +{
> > +	int timeout = HFC_TIMEOUT;
> > +	u8 mask = IDLL_RDY | PLL_RDY;
> > +	u8 regval;
> > +
> > +	do {
> > +		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
> > +		usleep_range(2000, 2500);
> 
> Any comment on how this delay value is obtained?

I don't have any specific comments, I believe the 2000us it taken from
the datasheet and the 2500 is us playing nice with the scheduler.

<snip>

> > +static inline int miphy365x_phy_rdy(struct miphy365x_phy *miphy_phy,
> > +				    struct miphy365x_dev *miphy_dev)
> > +{
> > +	int timeout = HFC_TIMEOUT;
> > +	u8 mask = mask = IDLL_RDY | PLL_RDY;
> 
> just u8 mask = IDLL_RDY | PLL_RDY; would suffice.

Hmm... not sure how this slipped through - will fix.

> > +	u8 regval;
> > +
> > +	do {
> > +		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
> > +		usleep_range(2000, 2500);
> 
> same here.

As above.

<snip>

> > +	mask = DES_BIT_LOCK | DES_SYMBOL_LOCK;
> > +	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask)	!= mask)
> > +		cpu_relax();
> 
> Don't we need to break from here at some point if the LOCK's are never set?

I'm sure sure that's possible, but I will invesigate and fixup if req'd.

<snip>

> > +static int miphy365x_phy_power_on(struct phy *phy)
> > +{
> > +	return 0;
> > +}
> > +
> > +static int miphy365x_phy_power_off(struct phy *phy)
> > +{
> > +	return 0;
> > +}
> 
> Both these empty functions can be removed.

You're right, I see the NULL checks, thanks.

<snip>

> > +static int miphy365x_phy_get_base_addr(struct platform_device *pdev,
> > +				       struct miphy365x_phy *phy, u8 port)
> > +{
> > +	struct resource *res;
> > +	char sata[16];
> > +	char pcie[16];
> 
> It can be done with a single variable ;-)

Right. :)

<snip>

> Phy provider register should be the last step in registering the PHY.

Okay, will fix, thanks.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH 4/4] phy: miphy365x: Provide support for the MiPHY356x Generic PHY

[Lee Jones]

> > The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> > devices. It has 2 ports which it can use for either; both SATA, both
> > PCIe or one of each in any configuration.
> >
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> >  drivers/phy/Kconfig         |   8 +
> >  drivers/phy/Makefile        |   1 +
> >  drivers/phy/phy-miphy365x.c | 634 ++++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 643 insertions(+)
> >  create mode 100644 drivers/phy/phy-miphy365x.c
> >
> 
> [...]
> 
> > +static int miphy365x_phy_get_base_addr(struct platform_device *pdev,
> > +                                      struct miphy365x_phy *phy, u8 port)
> > +{
> > +       struct resource *res;
> > +       char sata[16];
> > +       char pcie[16];
> 
> Isn't 6 enough for either of these? There are at most two ports IIUC, so
> we only need a single character for the port number.

Yep, being a bit overzealous there, will fix.

<snip>

> > +
> > +       of_property_read_string(np, "st,sata_gen", &sata_gen);
> 
> This wasn't in the binding documentation. It also violates dt style;
> s/_/-/

No problem, will fix.

> Could these not be numbers, or can this not come from elsewhere?
> 
> Or are there some crazy SATA generations to support?

Nope, just [1|2|3] I think. Can be numbers, will fix.

> > +       if (sata_gen) {
> > +               if (!strcmp(sata_gen, "gen3"))
> > +                       phy_dev->sata_gen = SATA_GEN3;
> > +               else if (!strcmp(sata_gen, "gen2"))
> > +                       phy_dev->sata_gen = SATA_GEN2;
> > +       }
> > +
> > +       phy_dev->pcie_tx_pol_inv =
> > +               of_property_read_bool(np, "st,pcie_tx_pol_inv");
> > +
> > +       phy_dev->sata_tx_pol_inv =
> > +               of_property_read_bool(np, "st,sata_tx_pol_inv");
> 
> Likewise for both of these on the first two points.

1. Roger will fix.

2. Not probeable I'm afraid.

> > +
> > +       return 0;
> > +}
> > +
> > +static int miphy365x_phy_probe(struct platform_device *pdev)
> > +{
> > +       struct device_node *np = pdev->dev.of_node;
> > +       struct miphy365x_dev *phy_dev;
> > +       struct device *dev = &pdev->dev;
> > +       struct phy_provider *provider;
> > +       u8 port;
> > +       int ret;
> > +
> > +       if (!np) {
> > +               dev_err(dev, "No DT found\n");
> 
> s/DT/node/ ?

s/DT/DT node/

Will fix, thanks.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x

[Lee Jones]

> > The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> > devices. It has 2 ports which it can use for either; both SATA, both
> > PCIe or one of each in any configuration.
> > 
> > Cc: devicetree at vger.kernel.org
> > Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> >  .../devicetree/bindings/phy/phy-miphy365x.txt      | 43 ++++++++++++++++++++++
> >  1 file changed, 43 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> > new file mode 100644
> > index 0000000..fdfa7ca
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> > @@ -0,0 +1,43 @@
> > +STMicroelectronics STi MIPHY365x PHY binding
> > +============================================
> > +
> > +This binding describes a miphy device that is used to control PHY hardware
> > +for SATA and PCIe.
> > +
> > +Required properties:
> > +- compatible: Should be "st,miphy365x-phy"
> > +- #phy-cells: Should be 2 (See example)
> 
> The first example has #phy-cells = <1>.

Right, will fix. Should be 2.

> What do the cells mean? What are the expected values?

http://www.spinics.net/lists/arm-kernel/msg307209.html

> > +- reg:	      Address and length of the register set for the device
> > +- reg-names:  The names of the register addresses corresponding to the
> > +	      registers filled in "reg".
> 
> Whenever there is a ${PROP}-names property, there should be a list of
> explicit values, and a description of how it relates to ${PROP}. Without
> that it's a bit useless.
> 
> Please provide an explicit list of expected names here.
> 
> I assume here what you want is something like:
> 
> - reg: a list of address + length pairs, one for each entry in reg-names
> - reg-names: should contain:
>   * "sata0" for the sata0 control registers...
>   * "sata1" ...
>   * "pcie0" ...
>   * "pcie1" ...

Can do.

> > +- st,syscfg : Should be a phandle of the syscfg node.
> 
> What's this used for?

It's used to gain access to the system configuration
registers. Specifically in this case the bits to choose between PCI or
SATA mode.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x

[Mark Rutland]

On Thu, Feb 13, 2014 at 11:03:14AM +0000, Lee Jones wrote:
> > > The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
> > > devices. It has 2 ports which it can use for either; both SATA, both
> > > PCIe or one of each in any configuration.
> > > 
> > > Cc: devicetree at vger.kernel.org
> > > Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> > > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > > ---
> > >  .../devicetree/bindings/phy/phy-miphy365x.txt      | 43 ++++++++++++++++++++++
> > >  1 file changed, 43 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> > > 
> > > diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> > > new file mode 100644
> > > index 0000000..fdfa7ca
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> > > @@ -0,0 +1,43 @@
> > > +STMicroelectronics STi MIPHY365x PHY binding
> > > +============================================
> > > +
> > > +This binding describes a miphy device that is used to control PHY hardware
> > > +for SATA and PCIe.
> > > +
> > > +Required properties:
> > > +- compatible: Should be "st,miphy365x-phy"
> > > +- #phy-cells: Should be 2 (See example)
> > 
> > The first example has #phy-cells = <1>.
> 
> Right, will fix. Should be 2.
> 
> > What do the cells mean? What are the expected values?
> 
> http://www.spinics.net/lists/arm-kernel/msg307209.html

Ok. Could that be mentioned in the binding document then?

Cheers,
Mark.

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Lee Jones]

This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).

Cc: devicetree at vger.kernel.org
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
new file mode 100644
index 0000000..8757c02
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy365x.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics miphy365x.
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+
+/* Supports 16 ports without a datatype change (u8 & 0xF0). */
+#define MIPHY_PORT_0			0
+#define MIPHY_PORT_1			1
+#define MIPHY_PORT_2			2
+#define MIPHY_PORT_3			3
+
+/* Supports 16 types without a datatype change (u8 & 0x0F). */
+#define MIPHY_TYPE_SHIFT		4
+#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
+
+#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
+#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
+#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
+#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)
+
+#endif /* _DT_BINDINGS_PHY_MIPHY */
-- 
1.8.3.2

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Mark Rutland]

On Fri, Feb 14, 2014 at 11:23:54AM +0000, Lee Jones wrote:
> This provides the shared header file which will be reference from both
> the MiPHY365x driver and its associated Device Tree node(s).
> 
> Cc: devicetree at vger.kernel.org
> Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
>  include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>  create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

Given this defines part of the binding, it should probably go in the
same patch.

Cheers,
Mark.

> 
> diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
> new file mode 100644
> index 0000000..8757c02
> --- /dev/null
> +++ b/include/dt-bindings/phy/phy-miphy365x.h
> @@ -0,0 +1,25 @@
> +/*
> + * This header provides constants for the phy framework
> + * based on the STMicroelectronics miphy365x.
> + */
> +#ifndef _DT_BINDINGS_PHY_MIPHY
> +#define _DT_BINDINGS_PHY_MIPHY
> +
> +/* Supports 16 ports without a datatype change (u8 & 0xF0). */
> +#define MIPHY_PORT_0			0
> +#define MIPHY_PORT_1			1
> +#define MIPHY_PORT_2			2
> +#define MIPHY_PORT_3			3
> +
> +/* Supports 16 types without a datatype change (u8 & 0x0F). */
> +#define MIPHY_TYPE_SHIFT		4
> +#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
> +#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
> +#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
> +
> +#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
> +#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
> +#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
> +#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)
> +
> +#endif /* _DT_BINDINGS_PHY_MIPHY */
> -- 
> 1.8.3.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Lee Jones]

This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
new file mode 100644
index 0000000..8757c02
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy365x.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics miphy365x.
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+
+/* Supports 16 ports without a datatype change (u8 & 0xF0). */
+#define MIPHY_PORT_0			0
+#define MIPHY_PORT_1			1
+#define MIPHY_PORT_2			2
+#define MIPHY_PORT_3			3
+
+/* Supports 16 types without a datatype change (u8 & 0x0F). */
+#define MIPHY_TYPE_SHIFT		4
+#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
+
+#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
+#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
+#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
+#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)
+
+#endif /* _DT_BINDINGS_PHY_MIPHY */
-- 
1.8.3.2

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Lee Jones]

This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
new file mode 100644
index 0000000..8757c02
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy365x.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics miphy365x.
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+
+/* Supports 16 ports without a datatype change (u8 & 0xF0). */
+#define MIPHY_PORT_0			0
+#define MIPHY_PORT_1			1
+#define MIPHY_PORT_2			2
+#define MIPHY_PORT_3			3
+
+/* Supports 16 types without a datatype change (u8 & 0x0F). */
+#define MIPHY_TYPE_SHIFT		4
+#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
+
+#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
+#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
+#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
+#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)
+
+#endif /* _DT_BINDINGS_PHY_MIPHY */
-- 
1.8.3.2

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Lee Jones]

This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
new file mode 100644
index 0000000..8757c02
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy365x.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics miphy365x.
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+
+/* Supports 16 ports without a datatype change (u8 & 0xF0). */
+#define MIPHY_PORT_0			0
+#define MIPHY_PORT_1			1
+#define MIPHY_PORT_2			2
+#define MIPHY_PORT_3			3
+
+/* Supports 16 types without a datatype change (u8 & 0x0F). */
+#define MIPHY_TYPE_SHIFT		4
+#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
+#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
+
+#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
+#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
+#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
+#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)
+
+#endif /* _DT_BINDINGS_PHY_MIPHY */
-- 
1.8.3.2

[PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines

[Sergei Shtylyov]

Hello.

On 05/22/2014 05:53 PM, Lee Jones wrote:

> This provides the shared header file which will be reference from both
> the MiPHY365x driver and its associated Device Tree node(s).

> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
>   include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>   create mode 100644 include/dt-bindings/phy/phy-miphy365x.h

> diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
> new file mode 100644
> index 0000000..8757c02
> --- /dev/null
> +++ b/include/dt-bindings/phy/phy-miphy365x.h
> @@ -0,0 +1,25 @@
> +/*
> + * This header provides constants for the phy framework
> + * based on the STMicroelectronics miphy365x.
> + */
> +#ifndef _DT_BINDINGS_PHY_MIPHY
> +#define _DT_BINDINGS_PHY_MIPHY
> +
> +/* Supports 16 ports without a datatype change (u8 & 0xF0). */
> +#define MIPHY_PORT_0			0
> +#define MIPHY_PORT_1			1
> +#define MIPHY_PORT_2			2
> +#define MIPHY_PORT_3			3
> +
> +/* Supports 16 types without a datatype change (u8 & 0x0F). */
> +#define MIPHY_TYPE_SHIFT		4
> +#define MIPHY_TYPE_SATA			(0 << MIPHY_TYPE_SHIFT)
> +#define MIPHY_TYPE_PCIE			(1 << MIPHY_TYPE_SHIFT)
> +#define MIPHY_TYPE_USB			(2 << MIPHY_TYPE_SHIFT)
> +
> +#define MIPHY_SATA_PORT0		(MIPHY_TYPE_SATA) | (MIPHY_PORT_0)
> +#define MIPHY_SATA_PORT1		(MIPHY_TYPE_SATA) | (MIPHY_PORT_1)
> +#define MIPHY_PCIE_PORT0		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_0)
> +#define MIPHY_PCIE_PORT1		(MIPHY_TYPE_PCIE) | (MIPHY_PORT_1)

    No need to have parens around macros but you should instead enclose the 
'|' operator and its arguments into parens.

WBR, Sergei