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[83.43.237.16]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50b36d23237sm150693321cf.13.2026.03.24.17.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 17:22:44 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Chen-Yu Tsai Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] dt-bindings: sram: Document Allwinner H616 VE SRAM Date: Wed, 25 Mar 2026 01:22:42 +0100 Message-ID: <13973231.uLZWGnKmhe@jernej-laptop> In-Reply-To: <20260324164357.1607247-2-wens@kernel.org> References: <20260324164357.1607247-1-wens@kernel.org> <20260324164357.1607247-2-wens@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260324_172247_299289_837C4F01 X-CRM114-Status: GOOD ( 13.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne torek, 24. marec 2026 ob 17:43:49 Srednjeevropski standardni =C4=8Das j= e Chen-Yu Tsai napisal(a): > The Allwinner H616 has two switchable peripheral SRAM regions: >=20 > - The VE SRAM is a 2 MB dedicated SRAM for the Video Engine. CPU access > to this region is enabled by default. CPU access can be disabled, > after which reads will show the same stale value for all addresses, > while writes are ignored. >=20 > The mux value for this region is different from previous generations, > and thus needs a completely new compatible. >=20 > - The SRAM C region is an alias of the first 128 KB of VE SRAM, plus 64 > KB of DE SRAM. The latter is otherwise unaccessible from the CPU. When > CPU access is disabled, the whole region reads as zero, while writes > are ignored. >=20 > The mux value for this region is the same as on the A64 and H6. The > existing compatible for the A64 already covers this. >=20 > Add the compatible for the VE SRAM to the list of covered compatibles in > the generic SRAM region binding. >=20 > Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec Best regards, Jernej