From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/8] ARM: cacheflush: use -st dsb option for ensuring completion
Date: Fri, 2 May 2014 16:24:08 +0100 [thread overview]
Message-ID: <1399044255-20435-2-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1399044255-20435-1-git-send-email-will.deacon@arm.com>
dsb st can be used to ensure completion of pending cache maintenance
operations, so use it for the v7 cache maintenance operations.
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/cacheflush.h | 2 +-
arch/arm/mm/cache-v7.S | 12 ++++++------
arch/arm/mm/mmu.c | 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 8b8b61685a34..00af9fe435e6 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
static inline void __flush_icache_all(void)
{
__flush_icache_preferred();
- dsb();
+ dsb(ishst);
}
/*
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 778bcf88ee79..615c99e38ba1 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1)
bgt 2b
cmp r2, #0
bgt 1b
- dsb
+ dsb st
isb
mov pc, lr
ENDPROC(v7_invalidate_l1)
@@ -166,7 +166,7 @@ skip:
finished:
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- dsb
+ dsb st
isb
mov pc, lr
ENDPROC(v7_flush_dcache_all)
@@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area)
add r0, r0, r2
cmp r0, r1
blo 1b
- dsb
+ dsb st
mov pc, lr
ENDPROC(v7_flush_kern_dcache_area)
@@ -368,7 +368,7 @@ v7_dma_inv_range:
add r0, r0, r2
cmp r0, r1
blo 1b
- dsb
+ dsb st
mov pc, lr
ENDPROC(v7_dma_inv_range)
@@ -390,7 +390,7 @@ v7_dma_clean_range:
add r0, r0, r2
cmp r0, r1
blo 1b
- dsb
+ dsb st
mov pc, lr
ENDPROC(v7_dma_clean_range)
@@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range)
add r0, r0, r2
cmp r0, r1
blo 1b
- dsb
+ dsb st
mov pc, lr
ENDPROC(v7_dma_flush_range)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b68c6b22e1c8..2b001e5dce87 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1461,7 +1461,7 @@ void __init early_paging_init(const struct machine_desc *mdesc,
* just complicate the code.
*/
flush_cache_louis();
- dsb();
+ dsb(ishst);
isb();
/* remap level 1 table */
--
1.9.2
next prev parent reply other threads:[~2014-05-02 15:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-02 15:24 [PATCH 0/8] ARM/arm64 Barrier cleanups and fixes for 3.16 Will Deacon
2014-05-02 15:24 ` Will Deacon [this message]
2014-05-02 15:24 ` [PATCH 2/8] ARM: cache: remove redundant dsb instruction from v7_coherent_user_range Will Deacon
2014-05-09 16:16 ` Catalin Marinas
2014-05-09 18:25 ` Will Deacon
2014-05-02 15:24 ` [PATCH 3/8] arm64: barriers: make use of barrier options with explicit barriers Will Deacon
2014-05-02 15:24 ` [PATCH 4/8] arm64: barriers: wire up new barrier options Will Deacon
2014-05-02 15:24 ` [PATCH 5/8] arm64: barriers: use barrier() instead of smp_mb() when !SMP Will Deacon
2014-05-02 15:24 ` [PATCH 6/8] arm64: head: fix cache flushing and barriers in set_cpu_boot_mode_flag Will Deacon
2014-05-02 15:24 ` [PATCH 7/8] arm64: kvm: use inner-shareable barriers for inner-shareable maintenance Will Deacon
2014-05-02 15:24 ` [PATCH 8/8] arm64: mm: " Will Deacon
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