* [PATCH 0/5] enable HiX5HD2 SoC
@ 2014-05-12 1:30 Haojian Zhuang
2014-05-12 1:30 ` [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Haojian Zhuang @ 2014-05-12 1:30 UTC (permalink / raw)
To: linux-arm-kernel
Haifeng Yan (4):
ARM: debug: Rename Hi3716 to HI5XHD2
ARM: hisi: enable hix5hd2 SoC
ARM: hisi: Add hix5hd2 SoC support.
ARM: dts: Add hix5hd2-dkb dts file.
Haojian Zhuang (1):
ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig
arch/arm/Kconfig.debug | 20 ++--
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/hix5hd2-dkb.dts | 56 +++++++++++
arch/arm/boot/dts/hix5hd2.dtsi | 189 ++++++++++++++++++++++++++++++++++++++
arch/arm/configs/hi3xxx_defconfig | 1 +
arch/arm/mach-hisi/Kconfig | 13 ++-
arch/arm/mach-hisi/Makefile | 1 +
arch/arm/mach-hisi/core.h | 3 +
arch/arm/mach-hisi/headsmp.S | 39 ++++++++
arch/arm/mach-hisi/hisilicon.c | 31 +++++++
arch/arm/mach-hisi/hotplug.c | 36 ++++++++
arch/arm/mach-hisi/platsmp.c | 70 +++++++++++++-
12 files changed, 445 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts
create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi
create mode 100644 arch/arm/mach-hisi/headsmp.S
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 2014-05-12 1:30 [PATCH 0/5] enable HiX5HD2 SoC Haojian Zhuang @ 2014-05-12 1:30 ` Haojian Zhuang 2014-05-12 4:23 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 2/5] ARM: hisi: enable hix5hd2 SoC Haojian Zhuang ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Haojian Zhuang @ 2014-05-12 1:30 UTC (permalink / raw) To: linux-arm-kernel From: Haifeng Yan <yanhaifeng@gmail.com> Rename Hisilicon HI3716 to HI5XHD2. And it relies on ARCH_HI5XHD2 instead. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> --- arch/arm/Kconfig.debug | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5a311af..df930e5 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -215,14 +215,6 @@ choice Say Y here if you want kernel low-level debugging support on HI3620 UART. - config DEBUG_HI3716_UART - bool "Hisilicon Hi3716 Debug UART" - depends on ARCH_HI3xxx - select DEBUG_UART_PL01X - help - Say Y here if you want kernel low-level debugging support - on HI3716 UART. - config DEBUG_HIP04_UART bool "Hisilicon HiP04 Debug UART" depends on ARCH_HIP04 @@ -231,6 +223,14 @@ choice Say Y here if you want kernel low-level debugging support on HIP04 UART. + config DEBUG_HIX5HD2_UART + bool "Hisilicon Hix5hd2 Debug UART" + depends on ARCH_HIX5HD2 + select DEBUG_UART_PL01X + help + Say Y here if you want kernel low-level debugging support + on Hix5hd2 UART. + config DEBUG_HIGHBANK_UART bool "Kernel low-level debugging messages via Highbank UART" depends on ARCH_HIGHBANK @@ -1058,7 +1058,7 @@ config DEBUG_UART_PHYS default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \ ARCH_ORION5X default 0xf7fc9000 if DEBUG_BERLIN_UART - default 0xf8b00000 if DEBUG_HI3716_UART + default 0xf8b00000 if DEBUG_HIX5HD2_UART default 0xfcb00000 if DEBUG_HI3620_UART default 0xfe800000 if ARCH_IOP32X default 0xffc02000 if DEBUG_SOCFPGA_UART @@ -1101,7 +1101,7 @@ config DEBUG_UART_VIRT default 0xfe230000 if DEBUG_PICOXCELL_UART default 0xfe300000 if DEBUG_BCM_KONA_UART default 0xfe800000 if ARCH_IOP32X - default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART + default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART default 0xfeb24000 if DEBUG_RK3X_UART0 default 0xfeb26000 if DEBUG_RK3X_UART1 default 0xfeb30c00 if DEBUG_KEYSTONE_UART0 -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 2014-05-12 1:30 ` [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang @ 2014-05-12 4:23 ` Olof Johansson 0 siblings, 0 replies; 10+ messages in thread From: Olof Johansson @ 2014-05-12 4:23 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 12, 2014 at 09:30:32AM +0800, Haojian Zhuang wrote: > From: Haifeng Yan <yanhaifeng@gmail.com> > > Rename Hisilicon HI3716 to HI5XHD2. And it relies on ARCH_HI5XHD2 > instead. In general, we never rename platforms in the kernel. Why are you renaming in this case? What is HI5XHD2? All of this should already have been part of the patch description. -Olof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/5] ARM: hisi: enable hix5hd2 SoC 2014-05-12 1:30 [PATCH 0/5] enable HiX5HD2 SoC Haojian Zhuang 2014-05-12 1:30 ` [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang @ 2014-05-12 1:30 ` Haojian Zhuang 2014-05-12 4:23 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 3/5] ARM: hisi: Add hix5hd2 SoC support Haojian Zhuang ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Haojian Zhuang @ 2014-05-12 1:30 UTC (permalink / raw) To: linux-arm-kernel From: Haifeng Yan <yanhaifeng@gmail.com> Enable HiX5HD2 SoC. Add ARCH_HIX5HD2 to support Hisilicon x5hd2 SoCs. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> --- arch/arm/mach-hisi/Kconfig | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 0a5a49d..94b7ff1 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -10,14 +10,14 @@ if ARCH_HISI menu "Hisilicon platform type" config ARCH_HI3xxx - bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7 + bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL select PINCTRL_SINGLE help - Support for Hisilicon Hi36xx/Hi37xx SoC family + Support for Hisilicon Hi36xx SoC family config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7 @@ -28,6 +28,15 @@ config ARCH_HIP04 help Support for Hisilicon HiP04 SoC family +config ARCH_HIX5HD2 + bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7 + select CACHE_L2X0 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select PINCTRL + select PINCTRL_SINGLE + help + Support for Hisilicon X5HD2 SoC family endmenu endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/5] ARM: hisi: enable hix5hd2 SoC 2014-05-12 1:30 ` [PATCH 2/5] ARM: hisi: enable hix5hd2 SoC Haojian Zhuang @ 2014-05-12 4:23 ` Olof Johansson 0 siblings, 0 replies; 10+ messages in thread From: Olof Johansson @ 2014-05-12 4:23 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 12, 2014 at 09:30:33AM +0800, Haojian Zhuang wrote: > From: Haifeng Yan <yanhaifeng@gmail.com> > > Enable HiX5HD2 SoC. What's this SoC? Please provide a brief description of it with your patch. -Olof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/5] ARM: hisi: Add hix5hd2 SoC support. 2014-05-12 1:30 [PATCH 0/5] enable HiX5HD2 SoC Haojian Zhuang 2014-05-12 1:30 ` [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang 2014-05-12 1:30 ` [PATCH 2/5] ARM: hisi: enable hix5hd2 SoC Haojian Zhuang @ 2014-05-12 1:30 ` Haojian Zhuang 2014-05-12 4:34 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 4/5] ARM: dts: Add hix5hd2-dkb dts file Haojian Zhuang 2014-05-12 1:30 ` [PATCH 5/5] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig Haojian Zhuang 4 siblings, 1 reply; 10+ messages in thread From: Haojian Zhuang @ 2014-05-12 1:30 UTC (permalink / raw) To: linux-arm-kernel From: Haifeng Yan <yanhaifeng@gmail.com> Add SoC support for Hisilicon x5hd2 SoC. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> --- arch/arm/mach-hisi/Makefile | 1 + arch/arm/mach-hisi/core.h | 3 ++ arch/arm/mach-hisi/headsmp.S | 39 +++++++++++++++++++++++ arch/arm/mach-hisi/hisilicon.c | 31 +++++++++++++++++++ arch/arm/mach-hisi/hotplug.c | 36 ++++++++++++++++++++++ arch/arm/mach-hisi/platsmp.c | 70 ++++++++++++++++++++++++++++++++++++++++-- 6 files changed, 177 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-hisi/headsmp.S diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile index e7a8640..428daf6 100644 --- a/arch/arm/mach-hisi/Makefile +++ b/arch/arm/mach-hisi/Makefile @@ -3,5 +3,6 @@ # obj-y += hisilicon.o +obj-$(CONFIG_ARCH_HIX5HD2) += headsmp.o obj-$(CONFIG_MCPM) += platmcpm.o obj-$(CONFIG_SMP) += platsmp.o hotplug.o diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h index 1e60795..be15620 100644 --- a/arch/arm/mach-hisi/core.h +++ b/arch/arm/mach-hisi/core.h @@ -13,5 +13,8 @@ extern int hi3xxx_cpu_kill(unsigned int cpu); extern void hi3xxx_set_cpu(int cpu, bool enable); extern bool __init hip04_smp_init_ops(void); +extern void hix5hd2_secondary_startup(void); +extern struct smp_operations hix5hd2_smp_ops; +extern void hix5hd2_set_cpu(int cpu, bool enable); #endif diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S new file mode 100644 index 0000000..c4b2a95 --- /dev/null +++ b/arch/arm/mach-hisi/headsmp.S @@ -0,0 +1,39 @@ +/* + * + * arch/arm/mach-hisi/headsmp.S + * + * Copyright (c) 2014 Hisilicon Limited. + * Copyright (c) 2014 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __CPUINIT + +ENTRY(hix5hd2_secondary_startup) + + /* set the cpu to SVC32 mode */ + mrs r0, cpsr + bic r0, r0, #0x1f /* r0 = ((~0x1F) & r0) */ + orr r0, r0, #0xd3 /* r0 = (0xd3 | r0) */ + msr cpsr, r0 + + /* disable MMU stuff and caches */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00002000 /* clear bits 13 (--V-) */ + bic r0, r0, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r0, r0, #0x00000002 /* set bit 1 (--A-) Align */ + orr r0, r0, #0x00000800 /* set bit 12 (Z---) BTB */ + mcr p15, 0, r0, c1, c0, 0 + + /* + * Invalidate L1 I/D + */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + bl v7_invalidate_l1 + b secondary_startup diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c index 6489e57..deaac5b 100644 --- a/arch/arm/mach-hisi/hisilicon.c +++ b/arch/arm/mach-hisi/hisilicon.c @@ -26,6 +26,8 @@ #define HI3620_SYSCTRL_PHYS_BASE 0xfc802000 #define HI3620_SYSCTRL_VIRT_BASE 0xfe802000 +#define HIX5HD2_SYSCTRL_PHYS_BASE 0xf8000000 +#define HIX5HD2_SYSCTRL_VIRT_BASE 0xfe802000 /* * This table is only for optimization. Since ioremap() could always share @@ -45,6 +47,16 @@ static struct map_desc hi3620_io_desc[] __initdata = { }, }; +static struct map_desc hix5hd2_io_desc[] __initdata = { + { + /* sysctrl */ + .pfn = __phys_to_pfn(HIX5HD2_SYSCTRL_PHYS_BASE), + .virtual = HIX5HD2_SYSCTRL_VIRT_BASE, + .length = 0x1000, + .type = MT_DEVICE, + }, +}; + static void __init hi3620_map_io(void) { debug_ll_io_init(); @@ -100,3 +112,22 @@ DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)") .smp_init = smp_init_ops(hip04_smp_init_ops), MACHINE_END #endif + +static void __init hix5hd2_map_io(void) +{ + debug_ll_io_init(); + iotable_init(hix5hd2_io_desc, ARRAY_SIZE(hix5hd2_io_desc)); +} + +/* hix5hd2 series */ +static const char *hix5hd2_compat[] __initconst = { + "hisilicon,hix5hd2-dkb", + NULL, +}; + +DT_MACHINE_START(HIX5HD2_DT, "Hisilicon X5HD2 (Flattened Device Tree)") + .map_io = hix5hd2_map_io, + .dt_compat = hix5hd2_compat, + .smp = smp_ops(hix5hd2_smp_ops), + .restart = hi3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c index abd441b..8599f57 100644 --- a/arch/arm/mach-hisi/hotplug.c +++ b/arch/arm/mach-hisi/hotplug.c @@ -57,6 +57,9 @@ #define CPU0_NEON_SRST_REQ_EN (1 << 4) #define CPU0_SRST_REQ_EN (1 << 0) +#define HIX5HD2_PERI_CRG20 0x50 +#define CRG20_CPU1_RESET (1 << 17) + enum { HI3620_CTRL, ERROR_CTRL, @@ -157,6 +160,39 @@ void hi3xxx_set_cpu(int cpu, bool enable) set_cpu_hi3620(cpu, enable); } +void hix5hd2_set_cpu(int cpu, bool enable) +{ + u32 val = 0; + + if (!ctrl_base) + BUG(); + + if (enable) { + /* power on cpu1 */ + val = readl_relaxed(ctrl_base + 0x1000); + val &= ~(0x1 << 8); + val |= (0x1 << 7); + val &= ~(0x1 << 3); + writel_relaxed(val, ctrl_base + 0x1000); + /* unreset */ + val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); + val &= ~CRG20_CPU1_RESET; + writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); + } else { + /* power down cpu1 */ + val = readl_relaxed(ctrl_base + 0x1000); + val &= ~(0x1 << 8); + val |= (0x1 << 7); + val |= (0x1 << 3); + writel_relaxed(val, ctrl_base + 0x1000); + + /* reset */ + val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); + val |= CRG20_CPU1_RESET; + writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); + } +} + static inline void cpu_enter_lowpower(void) { unsigned int v; diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index 471f1ee..3f83921 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -17,6 +17,8 @@ #include "core.h" +#define HIX5HD2_BOOT_ADDRESS 0xffff0000 + static void __iomem *ctrl_base; void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) @@ -35,11 +37,9 @@ int hi3xxx_get_cpu_jump(int cpu) return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); } -static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) +static void __init hisi_enable_scu_a9(void) { - struct device_node *np = NULL; unsigned long base = 0; - u32 offset = 0; void __iomem *scu_base = NULL; if (scu_a9_has_base()) { @@ -52,6 +52,14 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); iounmap(scu_base); } +} + +static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np = NULL; + u32 offset = 0; + + hisi_enable_scu_a9(); if (!ctrl_base) { np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); if (!np) { @@ -87,3 +95,59 @@ struct smp_operations hi3xxx_smp_ops __initdata = { .cpu_kill = hi3xxx_cpu_kill, #endif }; + +static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np = NULL; + + hisi_enable_scu_a9(); + + if (ctrl_base) + return; + np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl"); + if (np) { + ctrl_base = of_iomap(np, 0); + if (!ctrl_base) { + pr_err("failed to map address\n"); + return; + } + } +} + + +/* + * copy startup code to sram, and flash cache. + * @start_addr: slave start phy address + * @jump_addr: slave jump phy address + */ +void hix5hd2_set_scu_boot_addr(unsigned int start_addr, unsigned int jump_addr) +{ + void __iomem *virt; + + virt = ioremap(start_addr, PAGE_SIZE); + + *(unsigned int *)virt++ = 0xe51ff004; /* ldr pc, [pc, #-4] */ + *(unsigned int *)virt++ = jump_addr; /* pc jump phy address */ + iounmap(virt); +} + +static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned int jumpaddr; + + jumpaddr = (unsigned int)virt_to_phys(hix5hd2_secondary_startup); + hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); + hix5hd2_set_cpu(cpu, true); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; +} + + +struct smp_operations hix5hd2_smp_ops __initdata = { + .smp_prepare_cpus = hix5hd2_smp_prepare_cpus, + .smp_boot_secondary = hix5hd2_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = hi3xxx_cpu_die, + .cpu_kill = hi3xxx_cpu_kill, +#endif +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/5] ARM: hisi: Add hix5hd2 SoC support. 2014-05-12 1:30 ` [PATCH 3/5] ARM: hisi: Add hix5hd2 SoC support Haojian Zhuang @ 2014-05-12 4:34 ` Olof Johansson 0 siblings, 0 replies; 10+ messages in thread From: Olof Johansson @ 2014-05-12 4:34 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 12, 2014 at 09:30:34AM +0800, Haojian Zhuang wrote: > From: Haifeng Yan <yanhaifeng@gmail.com> > > Add SoC support for Hisilicon x5hd2 SoC. > > Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> > Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> > --- > arch/arm/mach-hisi/Makefile | 1 + > arch/arm/mach-hisi/core.h | 3 ++ > arch/arm/mach-hisi/headsmp.S | 39 +++++++++++++++++++++++ > arch/arm/mach-hisi/hisilicon.c | 31 +++++++++++++++++++ > arch/arm/mach-hisi/hotplug.c | 36 ++++++++++++++++++++++ > arch/arm/mach-hisi/platsmp.c | 70 ++++++++++++++++++++++++++++++++++++++++-- > 6 files changed, 177 insertions(+), 3 deletions(-) > create mode 100644 arch/arm/mach-hisi/headsmp.S > > diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile > index e7a8640..428daf6 100644 > --- a/arch/arm/mach-hisi/Makefile > +++ b/arch/arm/mach-hisi/Makefile > @@ -3,5 +3,6 @@ > # > > obj-y += hisilicon.o > +obj-$(CONFIG_ARCH_HIX5HD2) += headsmp.o > obj-$(CONFIG_MCPM) += platmcpm.o > obj-$(CONFIG_SMP) += platsmp.o hotplug.o > diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h > index 1e60795..be15620 100644 > --- a/arch/arm/mach-hisi/core.h > +++ b/arch/arm/mach-hisi/core.h > @@ -13,5 +13,8 @@ extern int hi3xxx_cpu_kill(unsigned int cpu); > extern void hi3xxx_set_cpu(int cpu, bool enable); > > extern bool __init hip04_smp_init_ops(void); > +extern void hix5hd2_secondary_startup(void); > +extern struct smp_operations hix5hd2_smp_ops; > +extern void hix5hd2_set_cpu(int cpu, bool enable); > > #endif > diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S > new file mode 100644 > index 0000000..c4b2a95 > --- /dev/null > +++ b/arch/arm/mach-hisi/headsmp.S > @@ -0,0 +1,39 @@ > +/* > + * > + * arch/arm/mach-hisi/headsmp.S File names in files don't make much sense. I know some platforms have them for legacy reasons, but let's not add new ones. > + */ > +#include <linux/linkage.h> > +#include <linux/init.h> > + > + __CPUINIT > + > +ENTRY(hix5hd2_secondary_startup) > + > + /* set the cpu to SVC32 mode */ > + mrs r0, cpsr > + bic r0, r0, #0x1f /* r0 = ((~0x1F) & r0) */ > + orr r0, r0, #0xd3 /* r0 = (0xd3 | r0) */ > + msr cpsr, r0 > + > + /* disable MMU stuff and caches */ > + mrc p15, 0, r0, c1, c0, 0 > + orr r0, r0, #0x00002000 /* clear bits 13 (--V-) */ > + bic r0, r0, #0x00000007 /* clear bits 2:0 (-CAM) */ > + orr r0, r0, #0x00000002 /* set bit 1 (--A-) Align */ > + orr r0, r0, #0x00000800 /* set bit 12 (Z---) BTB */ > + mcr p15, 0, r0, c1, c0, 0 > + > + /* > + * Invalidate L1 I/D > + */ > + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ > + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ > + bl v7_invalidate_l1 > + b secondary_startup > diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c > index 6489e57..deaac5b 100644 > --- a/arch/arm/mach-hisi/hisilicon.c > +++ b/arch/arm/mach-hisi/hisilicon.c > @@ -26,6 +26,8 @@ > > #define HI3620_SYSCTRL_PHYS_BASE 0xfc802000 > #define HI3620_SYSCTRL_VIRT_BASE 0xfe802000 > +#define HIX5HD2_SYSCTRL_PHYS_BASE 0xf8000000 > +#define HIX5HD2_SYSCTRL_VIRT_BASE 0xfe802000 > > /* > * This table is only for optimization. Since ioremap() could always share > @@ -45,6 +47,16 @@ static struct map_desc hi3620_io_desc[] __initdata = { > }, > }; > > +static struct map_desc hix5hd2_io_desc[] __initdata = { > + { > + /* sysctrl */ > + .pfn = __phys_to_pfn(HIX5HD2_SYSCTRL_PHYS_BASE), > + .virtual = HIX5HD2_SYSCTRL_VIRT_BASE, > + .length = 0x1000, > + .type = MT_DEVICE, > + }, This already has an entry in the DT, you shouldn't need a io_desc for it? > diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c > index abd441b..8599f57 100644 > --- a/arch/arm/mach-hisi/hotplug.c > +++ b/arch/arm/mach-hisi/hotplug.c > @@ -57,6 +57,9 @@ > #define CPU0_NEON_SRST_REQ_EN (1 << 4) > #define CPU0_SRST_REQ_EN (1 << 0) > > +#define HIX5HD2_PERI_CRG20 0x50 > +#define CRG20_CPU1_RESET (1 << 17) > + > enum { > HI3620_CTRL, > ERROR_CTRL, > @@ -157,6 +160,39 @@ void hi3xxx_set_cpu(int cpu, bool enable) > set_cpu_hi3620(cpu, enable); > } > > +void hix5hd2_set_cpu(int cpu, bool enable) > +{ > + u32 val = 0; > + > + if (!ctrl_base) > + BUG(); > + > + if (enable) { > + /* power on cpu1 */ > + val = readl_relaxed(ctrl_base + 0x1000); > + val &= ~(0x1 << 8); > + val |= (0x1 << 7); > + val &= ~(0x1 << 3); > + writel_relaxed(val, ctrl_base + 0x1000); > + /* unreset */ > + val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); > + val &= ~CRG20_CPU1_RESET; > + writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); > + } else { > + /* power down cpu1 */ > + val = readl_relaxed(ctrl_base + 0x1000); > + val &= ~(0x1 << 8); > + val |= (0x1 << 7); > + val |= (0x1 << 3); > + writel_relaxed(val, ctrl_base + 0x1000); > + > + /* reset */ > + val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); > + val |= CRG20_CPU1_RESET; > + writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); > + } > +} > + > static inline void cpu_enter_lowpower(void) > { > unsigned int v; > diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c > index 471f1ee..3f83921 100644 > --- a/arch/arm/mach-hisi/platsmp.c > +++ b/arch/arm/mach-hisi/platsmp.c > @@ -17,6 +17,8 @@ > > #include "core.h" > > +#define HIX5HD2_BOOT_ADDRESS 0xffff0000 > + > static void __iomem *ctrl_base; > > void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) > @@ -35,11 +37,9 @@ int hi3xxx_get_cpu_jump(int cpu) > return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); > } > > -static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) > +static void __init hisi_enable_scu_a9(void) > { > - struct device_node *np = NULL; > unsigned long base = 0; > - u32 offset = 0; > void __iomem *scu_base = NULL; > > if (scu_a9_has_base()) { > @@ -52,6 +52,14 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) > scu_enable(scu_base); > iounmap(scu_base); > } > +} > + > +static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) > +{ > + struct device_node *np = NULL; > + u32 offset = 0; > + > + hisi_enable_scu_a9(); > if (!ctrl_base) { > np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); > if (!np) { > @@ -87,3 +95,59 @@ struct smp_operations hi3xxx_smp_ops __initdata = { > .cpu_kill = hi3xxx_cpu_kill, > #endif > }; > + > +static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus) > +{ > + struct device_node *np = NULL; > + > + hisi_enable_scu_a9(); > + > + if (ctrl_base) > + return; > + np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl"); I don't see this documented anywhere. This needs a binding doc. > + if (np) { > + ctrl_base = of_iomap(np, 0); > + if (!ctrl_base) { > + pr_err("failed to map address\n"); > + return; > + } > + } > +} > + > + > +/* > + * copy startup code to sram, and flash cache. 'flush' cache? I don't see you flushing cache here anywhere. > + * @start_addr: slave start phy address > + * @jump_addr: slave jump phy address > + */ > +void hix5hd2_set_scu_boot_addr(unsigned int start_addr, unsigned int jump_addr) > +{ > + void __iomem *virt; > + > + virt = ioremap(start_addr, PAGE_SIZE); > + > + *(unsigned int *)virt++ = 0xe51ff004; /* ldr pc, [pc, #-4] */ > + *(unsigned int *)virt++ = jump_addr; /* pc jump phy address */ Ouch. If you ioremap, then you need to use the io accessors. No open coding like this. > + iounmap(virt); > +} > + > +static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle) > +{ > + unsigned int jumpaddr; phys_addr_t (then there's no need to cast below). > + jumpaddr = (unsigned int)virt_to_phys(hix5hd2_secondary_startup); > + hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); > + hix5hd2_set_cpu(cpu, true); Since you manually call set_cpu here, and just take two separate code paths through that function depending on the second argument, you might as well split it into two functions (hix5hd2_start_cpu() for this case, for example). -Olof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/5] ARM: dts: Add hix5hd2-dkb dts file. 2014-05-12 1:30 [PATCH 0/5] enable HiX5HD2 SoC Haojian Zhuang ` (2 preceding siblings ...) 2014-05-12 1:30 ` [PATCH 3/5] ARM: hisi: Add hix5hd2 SoC support Haojian Zhuang @ 2014-05-12 1:30 ` Haojian Zhuang 2014-05-12 4:40 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 5/5] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig Haojian Zhuang 4 siblings, 1 reply; 10+ messages in thread From: Haojian Zhuang @ 2014-05-12 1:30 UTC (permalink / raw) To: linux-arm-kernel From: Haifeng Yan <yanhaifeng@gmail.com> Add dts file for Hisilicon x5hd2 development kit board. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/hix5hd2-dkb.dts | 56 +++++++++++ arch/arm/boot/dts/hix5hd2.dtsi | 189 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 246 insertions(+) create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7119bca..54249d9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HIX5HD2) += hix5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb diff --git a/arch/arm/boot/dts/hix5hd2-dkb.dts b/arch/arm/boot/dts/hix5hd2-dkb.dts new file mode 100644 index 0000000..644458a --- /dev/null +++ b/arch/arm/boot/dts/hix5hd2-dkb.dts @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; +#include "hix5hd2.dtsi" + +/ { + model = "Hisilicon HiX5HD2 Development Board"; + compatible = "hisilicon,hix5hd2-dkb"; + + chosen { + bootargs = "console=ttyAMA0,115200"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu at 1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; + }; + + soc { + amba { + timer0: timer at f8002000 { + status = "okay"; + }; + + uart0: uart at f8b00000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/hix5hd2.dtsi b/arch/arm/boot/dts/hix5hd2.dtsi new file mode 100644 index 0000000..d8a3ad4 --- /dev/null +++ b/arch/arm/boot/dts/hix5hd2.dtsi @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/hix5hd2-clock.h> + +/ { + aliases { + serial0 = &uart0; + }; + + gic: interrupt-controller at f8a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&gic>; + ranges; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + ranges; + + timer0: timer at f8002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xf8002000 0x1000>; + /* timer00 & timer01 */ + interrupts = <0 24 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer1: timer at f8a29000 { + /* + * Only used in NORMAL state, not available ins + * SLOW or DOZE state. + * The rate is fixed in 24MHz. + */ + compatible = "arm,sp804", "arm,primecell"; + reg = <0xf8a29000 0x1000>; + /* timer10 & timer11 */ + interrupts = <0 25 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer2: timer at f8a2a000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xf8a2a000 0x1000>; + /* timer20 & timer21 */ + interrupts = <0 26 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer3: timer at f8a2b000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xf8a2b000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 27 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer4: timer at f8a81000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xf8a81000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 28 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + uart0: uart at f8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b00000 0x1000>; + interrupts = <0 49 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart1: uart at f8006000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8006000 0x1000>; + interrupts = <0 50 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: uart at f8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b02000 0x1000>; + interrupts = <0 51 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart3: uart at f8b03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b03000 0x1000>; + interrupts = <0 52 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart4: uart at f8b04000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b04000 0x1000>; + interrupts = <0 53 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + }; + + local_timer at f8a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + l2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xf8a10000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + hisilicon,l2cache-aux = <0x00050000 0xfff0ffff>; + }; + + /* unremovable emmc as mmcblk0 */ + dwmmc_1: dwmmc1 at f9830000 { + compatible = "hisilicon,hi3716-dw-mshc"; + reg = <0xf9830000 0x1000>; + interrupts = <0 35 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + + sctrl at f8000000 { + compatible = "hisilicon,sysctrl"; + reg = <0xf8000000 0x1000>; + smp_reg = <0xc0>; + reboot_reg = <0x4>; + }; + + clkbase at f8a22000 { + compatible = "hisilicon,clkbase"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8a22000 0x1000>; + ranges = <0x0 0xf8a22000 0x1000>; + clock: clock at 0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0x0 0x1000>; + #clock-cells = <1>; + }; + }; + + cpuctrl at f8a22000 { + compatible = "hisilicon,cpuctrl"; + reg = <0xf8a22000 0x2000>; + }; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/5] ARM: dts: Add hix5hd2-dkb dts file. 2014-05-12 1:30 ` [PATCH 4/5] ARM: dts: Add hix5hd2-dkb dts file Haojian Zhuang @ 2014-05-12 4:40 ` Olof Johansson 0 siblings, 0 replies; 10+ messages in thread From: Olof Johansson @ 2014-05-12 4:40 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 12, 2014 at 09:30:35AM +0800, Haojian Zhuang wrote: > From: Haifeng Yan <yanhaifeng@gmail.com> > > Add dts file for Hisilicon x5hd2 development kit board. > > Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> > Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> > --- > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/hix5hd2-dkb.dts | 56 +++++++++++ > arch/arm/boot/dts/hix5hd2.dtsi | 189 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 246 insertions(+) > create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts > create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 7119bca..54249d9 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ > exynos5440-sd5v1.dtb \ > exynos5440-ssdk5440.dtb > dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb > +dtb-$(CONFIG_ARCH_HIX5HD2) += hix5hd2-dkb.dtb > dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ > ecx-2000.dtb > dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb > diff --git a/arch/arm/boot/dts/hix5hd2-dkb.dts b/arch/arm/boot/dts/hix5hd2-dkb.dts > new file mode 100644 > index 0000000..644458a > --- /dev/null > +++ b/arch/arm/boot/dts/hix5hd2-dkb.dts > @@ -0,0 +1,56 @@ > +/* > + * Copyright (c) 2013 Linaro Ltd. > + * Copyright (c) 2013 Hisilicon Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * publishhed by the Free Software Foundation. > + */ > + > +/dts-v1/; > +#include "hix5hd2.dtsi" > + > +/ { > + model = "Hisilicon HiX5HD2 Development Board"; > + compatible = "hisilicon,hix5hd2-dkb"; This should have a compatible of the SoC as well (as less specific). > + chosen { > + bootargs = "console=ttyAMA0,115200"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu at 1 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000>; > + }; > + > + soc { > + amba { > + timer0: timer at f8002000 { > + status = "okay"; > + }; > + > + uart0: uart at f8b00000 { > + status = "okay"; > + }; This is much easier if you use a label-based syntax: &uart0 { status = "okay"; }; Then you don't need to mirror the hierarchy, etc. > diff --git a/arch/arm/boot/dts/hix5hd2.dtsi b/arch/arm/boot/dts/hix5hd2.dtsi > new file mode 100644 > index 0000000..d8a3ad4 > --- /dev/null > +++ b/arch/arm/boot/dts/hix5hd2.dtsi > @@ -0,0 +1,189 @@ > +/* > + * Copyright (c) 2013 Linaro Ltd. > + * Copyright (c) 2013 Hisilicon Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * publishhed by the Free Software Foundation. > + */ > + > +#include "skeleton.dtsi" > +#include <dt-bindings/clock/hix5hd2-clock.h> > + > +/ { You might want to add the compatible string here that will be shared for all boards of this platform. Each dts will of course override it, but it makes it easy for them to see what they should append to their more specific compatible values. > + aliases { > + serial0 = &uart0; > + }; > + > + gic: interrupt-controller at f8a01000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + /* gic dist base, gic cpu base */ > + reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + device_type = "soc"; > + interrupt-parent = <&gic>; > + ranges; > + > + amba { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "arm,amba-bus"; > + ranges; > + > + timer0: timer at f8002000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0xf8002000 0x1000>; > + /* timer00 & timer01 */ > + interrupts = <0 24 4>; > + clocks = <&clock HIX5HD2_FIXED_24M>; > + status = "disabled"; > + }; > + > + timer1: timer at f8a29000 { > + /* > + * Only used in NORMAL state, not available ins > + * SLOW or DOZE state. > + * The rate is fixed in 24MHz. > + */ > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0xf8a29000 0x1000>; > + /* timer10 & timer11 */ > + interrupts = <0 25 4>; > + clocks = <&clock HIX5HD2_FIXED_24M>; > + status = "disabled"; > + }; > + > + timer2: timer at f8a2a000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0xf8a2a000 0x1000>; > + /* timer20 & timer21 */ > + interrupts = <0 26 4>; > + clocks = <&clock HIX5HD2_FIXED_24M>; > + status = "disabled"; > + }; > + > + timer3: timer at f8a2b000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0xf8a2b000 0x1000>; > + /* timer30 & timer31 */ > + interrupts = <0 27 4>; > + clocks = <&clock HIX5HD2_FIXED_24M>; > + status = "disabled"; > + }; > + > + timer4: timer at f8a81000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0xf8a81000 0x1000>; > + /* timer30 & timer31 */ > + interrupts = <0 28 4>; > + clocks = <&clock HIX5HD2_FIXED_24M>; > + status = "disabled"; > + }; > + > + uart0: uart at f8b00000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0xf8b00000 0x1000>; > + interrupts = <0 49 4>; > + clocks = <&clock HIX5HD2_FIXED_83M>; > + clock-names = "apb_pclk"; > + status = "disabled"; > + }; > + > + uart1: uart at f8006000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0xf8006000 0x1000>; > + interrupts = <0 50 4>; > + clocks = <&clock HIX5HD2_FIXED_83M>; > + clock-names = "apb_pclk"; > + status = "disabled"; > + }; > + > + uart2: uart at f8b02000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0xf8b02000 0x1000>; > + interrupts = <0 51 4>; > + clocks = <&clock HIX5HD2_FIXED_83M>; > + clock-names = "apb_pclk"; > + status = "disabled"; > + }; > + > + uart3: uart at f8b03000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0xf8b03000 0x1000>; > + interrupts = <0 52 4>; > + clocks = <&clock HIX5HD2_FIXED_83M>; > + clock-names = "apb_pclk"; > + status = "disabled"; > + }; > + > + uart4: uart at f8b04000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0xf8b04000 0x1000>; > + interrupts = <0 53 4>; > + clocks = <&clock HIX5HD2_FIXED_83M>; > + clock-names = "apb_pclk"; > + status = "disabled"; > + }; > + }; > + > + local_timer at f8a00600 { local-timer > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0xf8a00600 0x20>; > + interrupts = <1 13 0xf01>; > + }; > + > + l2: l2-cache { > + compatible = "arm,pl310-cache"; > + reg = <0xf8a10000 0x100000>; > + interrupts = <0 15 4>; > + cache-unified; > + cache-level = <2>; > + hisilicon,l2cache-aux = <0x00050000 0xfff0ffff>; > + }; > + > + /* unremovable emmc as mmcblk0 */ > + dwmmc_1: dwmmc1 at f9830000 { The node name should be generic. Most other platforms use "mmc". No enumerating suffix in the node name. > + compatible = "hisilicon,hi3716-dw-mshc"; > + reg = <0xf9830000 0x1000>; > + interrupts = <0 35 4>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; > + clock-names = "ciu", "biu"; > + }; > + > + > + sctrl at f8000000 { system-controller > + compatible = "hisilicon,sysctrl"; > + reg = <0xf8000000 0x1000>; > + smp_reg = <0xc0>; > + reboot_reg = <0x4>; > + }; > + > + clkbase at f8a22000 { What's this? Needs a binding. Name should probably be something else too (clock-controller?) > + compatible = "hisilicon,clkbase"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0xf8a22000 0x1000>; > + ranges = <0x0 0xf8a22000 0x1000>; > + clock: clock at 0 { > + compatible = "hisilicon,hix5hd2-clock"; > + reg = <0x0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > + > + cpuctrl at f8a22000 { > + compatible = "hisilicon,cpuctrl"; > + reg = <0xf8a22000 0x2000>; > + }; Again, as pointed out in one of the other patches, this needs a binding. -Olof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 5/5] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig 2014-05-12 1:30 [PATCH 0/5] enable HiX5HD2 SoC Haojian Zhuang ` (3 preceding siblings ...) 2014-05-12 1:30 ` [PATCH 4/5] ARM: dts: Add hix5hd2-dkb dts file Haojian Zhuang @ 2014-05-12 1:30 ` Haojian Zhuang 4 siblings, 0 replies; 10+ messages in thread From: Haojian Zhuang @ 2014-05-12 1:30 UTC (permalink / raw) To: linux-arm-kernel Since both ARCH_HI3xxx and ARCH_HIX5HD2 are based on Cortex A9 & they're using similiar kernel features, make them share the same default config. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> --- arch/arm/configs/hi3xxx_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hi3xxx_defconfig index 553e1b6..132d8c8 100644 --- a/arch/arm/configs/hi3xxx_defconfig +++ b/arch/arm/configs/hi3xxx_defconfig @@ -5,6 +5,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_RD_LZMA=y CONFIG_ARCH_HISI=y CONFIG_ARCH_HI3xxx=y +CONFIG_ARCH_HIX5HD2=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2014-05-12 4:40 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-05-12 1:30 [PATCH 0/5] enable HiX5HD2 SoC Haojian Zhuang 2014-05-12 1:30 ` [PATCH 1/5] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang 2014-05-12 4:23 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 2/5] ARM: hisi: enable hix5hd2 SoC Haojian Zhuang 2014-05-12 4:23 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 3/5] ARM: hisi: Add hix5hd2 SoC support Haojian Zhuang 2014-05-12 4:34 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 4/5] ARM: dts: Add hix5hd2-dkb dts file Haojian Zhuang 2014-05-12 4:40 ` Olof Johansson 2014-05-12 1:30 ` [PATCH 5/5] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig Haojian Zhuang
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