* [PATCH v2 1/6] ARM: hisi: store reboot reg in global variable
2014-05-13 9:44 [PATCH v2 0/6] enable HiX5HD2 SoC Haojian Zhuang
@ 2014-05-13 9:44 ` Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 2/6] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Haojian Zhuang @ 2014-05-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Avoid to parse DT in restart() function. Parsing these in init_late()
instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
arch/arm/mach-hisi/hisilicon.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 6489e57..a476388 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -45,33 +45,38 @@ static struct map_desc hi3620_io_desc[] __initdata = {
},
};
+static void __iomem *sysctrl_base;
+static u32 reboot_offset;
+
static void __init hi3620_map_io(void)
{
debug_ll_io_init();
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
-static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
+static void __init hi3xxx_init_late(void)
{
struct device_node *np;
- void __iomem *base;
- int offset;
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
pr_err("failed to find hisilicon,sysctrl node\n");
return;
}
- base = of_iomap(np, 0);
- if (!base) {
+ sysctrl_base = of_iomap(np, 0);
+ if (!sysctrl_base) {
pr_err("failed to map address in hisilicon,sysctrl node\n");
return;
}
- if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
+ if (of_property_read_u32(np, "reboot-offset", &reboot_offset) < 0) {
pr_err("failed to find reboot-offset property\n");
return;
}
- writel_relaxed(0xdeadbeef, base + offset);
+}
+
+static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
+{
+ writel_relaxed(0xdeadbeef, sysctrl_base + reboot_offset);
while (1)
cpu_do_idle();
@@ -85,6 +90,7 @@ static const char *hi3xxx_compat[] __initconst = {
DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.map_io = hi3620_map_io,
.dt_compat = hi3xxx_compat,
+ .init_late = hi3xxx_init_late,
.smp = smp_ops(hi3xxx_smp_ops),
.restart = hi3xxx_restart,
MACHINE_END
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 2/6] ARM: debug: Rename Hi3716 to HI5XHD2
2014-05-13 9:44 [PATCH v2 0/6] enable HiX5HD2 SoC Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 1/6] ARM: hisi: store reboot reg in global variable Haojian Zhuang
@ 2014-05-13 9:44 ` Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 3/6] ARM: hisi: enable hix5hd2 SoC Haojian Zhuang
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Haojian Zhuang @ 2014-05-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Haifeng Yan <yanhaifeng@gmail.com>
Rename Hisilicon HI3716 to HI5XHD2. And it relies on ARCH_HI5XHD2
instead.
Hi5XHD2 is a SoC with dual Cortex A9 cores.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
arch/arm/Kconfig.debug | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5a311af..df930e5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -215,14 +215,6 @@ choice
Say Y here if you want kernel low-level debugging support
on HI3620 UART.
- config DEBUG_HI3716_UART
- bool "Hisilicon Hi3716 Debug UART"
- depends on ARCH_HI3xxx
- select DEBUG_UART_PL01X
- help
- Say Y here if you want kernel low-level debugging support
- on HI3716 UART.
-
config DEBUG_HIP04_UART
bool "Hisilicon HiP04 Debug UART"
depends on ARCH_HIP04
@@ -231,6 +223,14 @@ choice
Say Y here if you want kernel low-level debugging support
on HIP04 UART.
+ config DEBUG_HIX5HD2_UART
+ bool "Hisilicon Hix5hd2 Debug UART"
+ depends on ARCH_HIX5HD2
+ select DEBUG_UART_PL01X
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Hix5hd2 UART.
+
config DEBUG_HIGHBANK_UART
bool "Kernel low-level debugging messages via Highbank UART"
depends on ARCH_HIGHBANK
@@ -1058,7 +1058,7 @@ config DEBUG_UART_PHYS
default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
ARCH_ORION5X
default 0xf7fc9000 if DEBUG_BERLIN_UART
- default 0xf8b00000 if DEBUG_HI3716_UART
+ default 0xf8b00000 if DEBUG_HIX5HD2_UART
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfe800000 if ARCH_IOP32X
default 0xffc02000 if DEBUG_SOCFPGA_UART
@@ -1101,7 +1101,7 @@ config DEBUG_UART_VIRT
default 0xfe230000 if DEBUG_PICOXCELL_UART
default 0xfe300000 if DEBUG_BCM_KONA_UART
default 0xfe800000 if ARCH_IOP32X
- default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART
+ default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
default 0xfeb24000 if DEBUG_RK3X_UART0
default 0xfeb26000 if DEBUG_RK3X_UART1
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 3/6] ARM: hisi: enable hix5hd2 SoC
2014-05-13 9:44 [PATCH v2 0/6] enable HiX5HD2 SoC Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 1/6] ARM: hisi: store reboot reg in global variable Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 2/6] ARM: debug: Rename Hi3716 to HI5XHD2 Haojian Zhuang
@ 2014-05-13 9:44 ` Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 4/6] ARM: dts: Add hix5hd2-dkb dts file Haojian Zhuang
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Haojian Zhuang @ 2014-05-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Haifeng Yan <yanhaifeng@gmail.com>
Enable Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series support both
one core or dual cores. The core is Cortex A9.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
arch/arm/mach-hisi/Kconfig | 13 ++++++++--
arch/arm/mach-hisi/Makefile | 1 +
arch/arm/mach-hisi/core.h | 5 ++++
arch/arm/mach-hisi/headsmp.S | 36 ++++++++++++++++++++++++++
arch/arm/mach-hisi/hisilicon.c | 14 ++++++++++
arch/arm/mach-hisi/hotplug.c | 58 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-hisi/platsmp.c | 50 +++++++++++++++++++++++++++++++++---
7 files changed, 172 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/mach-hisi/headsmp.S
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 0a5a49d..94b7ff1 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -10,14 +10,14 @@ if ARCH_HISI
menu "Hisilicon platform type"
config ARCH_HI3xxx
- bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+ bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PINCTRL
select PINCTRL_SINGLE
help
- Support for Hisilicon Hi36xx/Hi37xx SoC family
+ Support for Hisilicon Hi36xx SoC family
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
@@ -28,6 +28,15 @@ config ARCH_HIP04
help
Support for Hisilicon HiP04 SoC family
+config ARCH_HIX5HD2
+ bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
+ select CACHE_L2X0
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select PINCTRL
+ select PINCTRL_SINGLE
+ help
+ Support for Hisilicon X5HD2 SoC family
endmenu
endif
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index e7a8640..428daf6 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -3,5 +3,6 @@
#
obj-y += hisilicon.o
+obj-$(CONFIG_ARCH_HIX5HD2) += headsmp.o
obj-$(CONFIG_MCPM) += platmcpm.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index 1e60795..5d19ebe 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -14,4 +14,9 @@ extern void hi3xxx_set_cpu(int cpu, bool enable);
extern bool __init hip04_smp_init_ops(void);
+extern void hix5hd2_secondary_startup(void);
+extern struct smp_operations hix5hd2_smp_ops;
+extern void hix5hd2_set_cpu(int cpu, bool enable);
+extern void hix5hd2_cpu_die(unsigned int cpu);
+
#endif
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
new file mode 100644
index 0000000..7947e91
--- /dev/null
+++ b/arch/arm/mach-hisi/headsmp.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2014 Hisilicon Limited.
+ * Copyright (c) 2014 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __CPUINIT
+
+ENTRY(hix5hd2_secondary_startup)
+
+ /* set the cpu to SVC32 mode */
+ mrs r0, cpsr
+ bic r0, r0, #0x1f /* r0 = ((~0x1F) & r0) */
+ orr r0, r0, #0xd3 /* r0 = (0xd3 | r0) */
+ msr cpsr, r0
+
+ /* disable MMU stuff and caches */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00002000 /* clear bits 13 (--V-) */
+ bic r0, r0, #0x00000007 /* clear bits 2:0 (-CAM) */
+ orr r0, r0, #0x00000002 /* set bit 1 (--A-) Align */
+ orr r0, r0, #0x00000800 /* set bit 12 (Z---) BTB */
+ mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * Invalidate L1 I/D
+ */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ bl v7_invalidate_l1
+ b secondary_startup
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index a476388..8255ce6 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -26,6 +26,8 @@
#define HI3620_SYSCTRL_PHYS_BASE 0xfc802000
#define HI3620_SYSCTRL_VIRT_BASE 0xfe802000
+#define HIX5HD2_SYSCTRL_PHYS_BASE 0xf8000000
+#define HIX5HD2_SYSCTRL_VIRT_BASE 0xfe802000
/*
* This table is only for optimization. Since ioremap() could always share
@@ -106,3 +108,15 @@ DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
.smp_init = smp_init_ops(hip04_smp_init_ops),
MACHINE_END
#endif
+
+static const char *hix5hd2_compat[] __initconst = {
+ "hisilicon,hix5hd2",
+ NULL,
+};
+
+DT_MACHINE_START(HIX5HD2_DT, "Hisilicon X5HD2 (Flattened Device Tree)")
+ .dt_compat = hix5hd2_compat,
+ .init_late = hi3xxx_init_late,
+ .smp = smp_ops(hix5hd2_smp_ops),
+ .restart = hi3xxx_restart,
+MACHINE_END
diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
index abd441b..84e6919 100644
--- a/arch/arm/mach-hisi/hotplug.c
+++ b/arch/arm/mach-hisi/hotplug.c
@@ -57,6 +57,14 @@
#define CPU0_NEON_SRST_REQ_EN (1 << 4)
#define CPU0_SRST_REQ_EN (1 << 0)
+#define HIX5HD2_PERI_CRG20 0x50
+#define CRG20_CPU1_RESET (1 << 17)
+
+#define HIX5HD2_PERI_PMC0 0x1000
+#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
+#define PMC0_CPU1_PMC_ENABLE (1 << 7)
+#define PMC0_CPU1_POWERDOWN (1 << 3)
+
enum {
HI3620_CTRL,
ERROR_CTRL,
@@ -157,6 +165,50 @@ void hi3xxx_set_cpu(int cpu, bool enable)
set_cpu_hi3620(cpu, enable);
}
+static bool hix5hd2_hotplug_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
+ if (np) {
+ ctrl_base = of_iomap(np, 0);
+ return true;
+ }
+ return false;
+}
+
+void hix5hd2_set_cpu(int cpu, bool enable)
+{
+ u32 val = 0;
+
+ if (!ctrl_base)
+ if (!hix5hd2_hotplug_init())
+ BUG();
+
+ if (enable) {
+ /* power on cpu1 */
+ val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
+ val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
+ val |= PMC0_CPU1_PMC_ENABLE;
+ writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
+ /* unreset */
+ val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
+ val &= ~CRG20_CPU1_RESET;
+ writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
+ } else {
+ /* power down cpu1 */
+ val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
+ val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
+ val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
+ writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
+
+ /* reset */
+ val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
+ val |= CRG20_CPU1_RESET;
+ writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
+ }
+}
+
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
@@ -199,4 +251,10 @@ int hi3xxx_cpu_kill(unsigned int cpu)
hi3xxx_set_cpu(cpu, false);
return 1;
}
+
+void hix5hd2_cpu_die(unsigned int cpu)
+{
+ flush_cache_all();
+ hix5hd2_set_cpu(cpu, false);
+}
#endif
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 471f1ee..ecf7058 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -17,6 +17,8 @@
#include "core.h"
+#define HIX5HD2_BOOT_ADDRESS 0xffff0000
+
static void __iomem *ctrl_base;
void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
@@ -35,11 +37,9 @@ int hi3xxx_get_cpu_jump(int cpu)
return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
}
-static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
+static void __init hisi_enable_scu_a9(void)
{
- struct device_node *np = NULL;
unsigned long base = 0;
- u32 offset = 0;
void __iomem *scu_base = NULL;
if (scu_a9_has_base()) {
@@ -52,6 +52,14 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
scu_enable(scu_base);
iounmap(scu_base);
}
+}
+
+static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *np = NULL;
+ u32 offset = 0;
+
+ hisi_enable_scu_a9();
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
@@ -87,3 +95,39 @@ struct smp_operations hi3xxx_smp_ops __initdata = {
.cpu_kill = hi3xxx_cpu_kill,
#endif
};
+
+static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus)
+{
+ hisi_enable_scu_a9();
+}
+
+void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
+{
+ void __iomem *virt;
+
+ virt = ioremap(start_addr, PAGE_SIZE);
+
+ writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
+ writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
+ iounmap(virt);
+}
+
+static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ phys_addr_t jumpaddr;
+
+ jumpaddr = virt_to_phys(hix5hd2_secondary_startup);
+ hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
+ hix5hd2_set_cpu(cpu, true);
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+ return 0;
+}
+
+
+struct smp_operations hix5hd2_smp_ops __initdata = {
+ .smp_prepare_cpus = hix5hd2_smp_prepare_cpus,
+ .smp_boot_secondary = hix5hd2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = hix5hd2_cpu_die,
+#endif
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 4/6] ARM: dts: Add hix5hd2-dkb dts file.
2014-05-13 9:44 [PATCH v2 0/6] enable HiX5HD2 SoC Haojian Zhuang
` (2 preceding siblings ...)
2014-05-13 9:44 ` [PATCH v2 3/6] ARM: hisi: enable hix5hd2 SoC Haojian Zhuang
@ 2014-05-13 9:44 ` Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 5/6] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 6/6] document: add dt binding on hix5hd2 SoC Haojian Zhuang
5 siblings, 0 replies; 7+ messages in thread
From: Haojian Zhuang @ 2014-05-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Haifeng Yan <yanhaifeng@gmail.com>
Add dts file for Hisilicon x5hd2 development kit board.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/hix5hd2-dkb.dts | 52 ++++++++++++
arch/arm/boot/dts/hix5hd2.dtsi | 171 ++++++++++++++++++++++++++++++++++++++
3 files changed, 224 insertions(+)
create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts
create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7119bca..54249d9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HIX5HD2) += hix5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
diff --git a/arch/arm/boot/dts/hix5hd2-dkb.dts b/arch/arm/boot/dts/hix5hd2-dkb.dts
new file mode 100644
index 0000000..d55738b
--- /dev/null
+++ b/arch/arm/boot/dts/hix5hd2-dkb.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "hix5hd2.dtsi"
+
+/ {
+ model = "Hisilicon HiX5HD2 Development Board";
+ compatible = "hisilicon,hix5hd2";
+
+ chosen {
+ bootargs = "console=ttyAMA0,115200 earlyprintk";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&l2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000>;
+ };
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/hix5hd2.dtsi b/arch/arm/boot/dts/hix5hd2.dtsi
new file mode 100644
index 0000000..73f9ac1
--- /dev/null
+++ b/arch/arm/boot/dts/hix5hd2.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hix5hd2-clock.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ gic: interrupt-controller at f8a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ /* gic dist base, gic cpu base */
+ reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0 0xf8000000 0x8000000>;
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ ranges;
+
+ timer0: timer at 00002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00002000 0x1000>;
+ /* timer00 & timer01 */
+ interrupts = <0 24 4>;
+ clocks = <&clock HIX5HD2_FIXED_24M>;
+ status = "disabled";
+ };
+
+ timer1: timer at 00a29000 {
+ /*
+ * Only used in NORMAL state, not available ins
+ * SLOW or DOZE state.
+ * The rate is fixed in 24MHz.
+ */
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00a29000 0x1000>;
+ /* timer10 & timer11 */
+ interrupts = <0 25 4>;
+ clocks = <&clock HIX5HD2_FIXED_24M>;
+ status = "disabled";
+ };
+
+ timer2: timer at 00a2a000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00a2a000 0x1000>;
+ /* timer20 & timer21 */
+ interrupts = <0 26 4>;
+ clocks = <&clock HIX5HD2_FIXED_24M>;
+ status = "disabled";
+ };
+
+ timer3: timer at 00a2b000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00a2b000 0x1000>;
+ /* timer30 & timer31 */
+ interrupts = <0 27 4>;
+ clocks = <&clock HIX5HD2_FIXED_24M>;
+ status = "disabled";
+ };
+
+ timer4: timer at 00a81000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00a81000 0x1000>;
+ /* timer30 & timer31 */
+ interrupts = <0 28 4>;
+ clocks = <&clock HIX5HD2_FIXED_24M>;
+ status = "disabled";
+ };
+
+ uart0: uart at 00b00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x00b00000 0x1000>;
+ interrupts = <0 49 4>;
+ clocks = <&clock HIX5HD2_FIXED_83M>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart1: uart at 00006000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x00006000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&clock HIX5HD2_FIXED_83M>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart2: uart at 00b02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x00b02000 0x1000>;
+ interrupts = <0 51 4>;
+ clocks = <&clock HIX5HD2_FIXED_83M>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart3: uart at 00b03000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x00b03000 0x1000>;
+ interrupts = <0 52 4>;
+ clocks = <&clock HIX5HD2_FIXED_83M>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart4: uart at 00b04000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0xb04000 0x1000>;
+ interrupts = <0 53 4>;
+ clocks = <&clock HIX5HD2_FIXED_83M>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ };
+
+ local_timer at 00a00600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x00a00600 0x20>;
+ interrupts = <1 13 0xf01>;
+ };
+
+ l2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a10000 0x100000>;
+ interrupts = <0 15 4>;
+ cache-unified;
+ cache-level = <2>;
+ hisilicon,l2cache-aux = <0x00050000 0xfff0ffff>;
+ };
+
+ sysctrl: system-controller at 00000000 {
+ compatible = "hisilicon,sysctrl";
+ reg = <0x00000000 0x1000>;
+ reboot-offset = <0x4>;
+ };
+
+ cpuctrl at 00a22000 {
+ compatible = "hisilicon,cpuctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00a22000 0x2000>;
+ ranges = <0 0x00a22000 0x2000>;
+
+ clock: clock at 0 {
+ compatible = "hisilicon,hix5hd2-clock";
+ reg = <0 0x2000>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 5/6] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig
2014-05-13 9:44 [PATCH v2 0/6] enable HiX5HD2 SoC Haojian Zhuang
` (3 preceding siblings ...)
2014-05-13 9:44 ` [PATCH v2 4/6] ARM: dts: Add hix5hd2-dkb dts file Haojian Zhuang
@ 2014-05-13 9:44 ` Haojian Zhuang
2014-05-13 9:44 ` [PATCH v2 6/6] document: add dt binding on hix5hd2 SoC Haojian Zhuang
5 siblings, 0 replies; 7+ messages in thread
From: Haojian Zhuang @ 2014-05-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Since both ARCH_HI3xxx and ARCH_HIX5HD2 are based on Cortex A9 & they're
using similiar kernel features, make them share the same default config.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
arch/arm/configs/hi3xxx_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hi3xxx_defconfig
index 553e1b6..132d8c8 100644
--- a/arch/arm/configs/hi3xxx_defconfig
+++ b/arch/arm/configs/hi3xxx_defconfig
@@ -5,6 +5,7 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_LZMA=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_HI3xxx=y
+CONFIG_ARCH_HIX5HD2=y
CONFIG_SMP=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 6/6] document: add dt binding on hix5hd2 SoC
2014-05-13 9:44 [PATCH v2 0/6] enable HiX5HD2 SoC Haojian Zhuang
` (4 preceding siblings ...)
2014-05-13 9:44 ` [PATCH v2 5/6] ARM: config: add ARCH_HIX5HD2 in hi3xxx_defconfig Haojian Zhuang
@ 2014-05-13 9:44 ` Haojian Zhuang
5 siblings, 0 replies; 7+ messages in thread
From: Haojian Zhuang @ 2014-05-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Add the DT binding of basic SoC on Hisilicon HiX5HD2 SoC.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 5024992..4b06c1e 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -7,6 +7,9 @@ Required root node properties:
HiP04 D01 Board
Required root node properties:
- compatible = "hisilicon,hip04-d01";
+HiX5HD2 DKB Board
+Required root node properties:
+ - compatible = "hisilicon,hix5hd2";
Hisilicon system controller
@@ -65,3 +68,9 @@ Fabric:
Required Properties:
- compatible: "hisilicon,hip04-fabric";
- reg: Address and size of Fabric
+
+Cpu power controller:
+
+Required Properties:
+- compatible: "hisilicon,cpuctrl";
+- reg: Address and size of cpu power controller.
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread