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From: ritesh.harjani@gmail.com (ritesh.harjani at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/1] Implement flush_kern_tlb_page
Date: Mon, 19 May 2014 16:04:24 +0530	[thread overview]
Message-ID: <1400495665-48279-1-git-send-email-ritesh.harjani@gmail.com> (raw)

From: Ritesh Harjani <ritesh.harjani@gmail.com>

This patch adds the function definition to
flush_kern_tlb_page, defined in comments header in
arch/arm64/include/asm/tlbflush.h

>From ARMv8_arm: 
TLBI VAE1IS: Global TLB entries that match the VA value will be affected by this operation,
regardless of the value of the ASID field.


So, since kernel region has nG(non-Global) == 0, means region is available for
all processes. So, we can use TLBI VAE1IS for kernel region as well. 

Ritesh Harjani (1):
  arm64: TLB maintainance: Implement flush_kern_tlb_page

 arch/arm64/include/asm/tlbflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
1.8.1.3

             reply	other threads:[~2014-05-19 10:34 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-19 10:34 ritesh.harjani at gmail.com [this message]
2014-05-19 10:34 ` [PATCH 1/1] arm64: TLB maintainance: Implement flush_kern_tlb_page ritesh.harjani at gmail.com
2014-05-19 10:46   ` Catalin Marinas
2014-05-19 10:54     ` Ritesh Harjani
2014-05-19 11:01       ` Catalin Marinas
2014-05-19 11:07         ` Ritesh Harjani

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