[PATCH 0/1] Implement flush_kern_tlb_page

[PATCH 0/1] Implement flush_kern_tlb_page

[ritesh.harjani at gmail.com]

From: Ritesh Harjani <ritesh.harjani@gmail.com>

This patch adds the function definition to
flush_kern_tlb_page, defined in comments header in
arch/arm64/include/asm/tlbflush.h

>From ARMv8_arm: 
TLBI VAE1IS: Global TLB entries that match the VA value will be affected by this operation,
regardless of the value of the ASID field.


So, since kernel region has nG(non-Global) == 0, means region is available for
all processes. So, we can use TLBI VAE1IS for kernel region as well. 

Ritesh Harjani (1):
  arm64: TLB maintainance: Implement flush_kern_tlb_page

 arch/arm64/include/asm/tlbflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
1.8.1.3

[PATCH 1/1] arm64: TLB maintainance: Implement flush_kern_tlb_page

[ritesh.harjani at gmail.com]

From: Ritesh Harjani <ritesh.harjani@gmail.com>

Implement flush_kern_tlb_page mentioned in the header
comment of arch/arm64/include/asm/tlbflush.h

Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com>
---
 arch/arm64/include/asm/tlbflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 8b48203..92d0588 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -98,6 +98,16 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
 	dsb();
 }
 
+static inline void flush_kern_tlb_page(unsigned long kaddr)
+{
+	unsigned long addr = kaddr >> 12;
+
+	dsb();
+	asm("tlbi	vae1is, %0" : : "r" (addr));
+	dsb();
+	isb();
+}
+
 /*
  * Convert calls to our calling convention.
  */
-- 
1.8.1.3

[PATCH 1/1] arm64: TLB maintainance: Implement flush_kern_tlb_page

[Catalin Marinas]

On Mon, May 19, 2014 at 11:34:25AM +0100, ritesh.harjani at gmail.com wrote:
> From: Ritesh Harjani <ritesh.harjani@gmail.com>
> 
> Implement flush_kern_tlb_page mentioned in the header
> comment of arch/arm64/include/asm/tlbflush.h

Alternatively, clean-up the comment.

-- 
Catalin

[PATCH 1/1] arm64: TLB maintainance: Implement flush_kern_tlb_page

[Ritesh Harjani]

Hi Catalin,

On Mon, May 19, 2014 at 4:16 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Mon, May 19, 2014 at 11:34:25AM +0100, ritesh.harjani at gmail.com wrote:
>> From: Ritesh Harjani <ritesh.harjani@gmail.com>
>>
>> Implement flush_kern_tlb_page mentioned in the header
>> comment of arch/arm64/include/asm/tlbflush.h
>
> Alternatively, clean-up the comment.

You mean this function is of no use ? Or there are other plans which
might require clean up of this file ?

Also, could you please confirm whether the implementation of the
function is correct ?

>> +       asm("tlbi       vae1is, %0" : : "r" (addr));

Should following instruction be more appropriate instead of above:
asm("tlbi       vaae1is, %0" : : "r" (addr));

>
> --
> Catalin


Thanks
Ritesh

[PATCH 1/1] arm64: TLB maintainance: Implement flush_kern_tlb_page

[Catalin Marinas]

On Mon, May 19, 2014 at 11:54:31AM +0100, Ritesh Harjani wrote:
> On Mon, May 19, 2014 at 4:16 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Mon, May 19, 2014 at 11:34:25AM +0100, ritesh.harjani at gmail.com wrote:
> >> From: Ritesh Harjani <ritesh.harjani@gmail.com>
> >>
> >> Implement flush_kern_tlb_page mentioned in the header
> >> comment of arch/arm64/include/asm/tlbflush.h
> >
> > Alternatively, clean-up the comment.
> 
> You mean this function is of no use ? Or there are other plans which
> might require clean up of this file ?

Since we don't have it and the kernel builds fine, I guess we don't need
it.

> Also, could you please confirm whether the implementation of the
> function is correct ?
> 
> >> +       asm("tlbi       vae1is, %0" : : "r" (addr));
> 
> Should following instruction be more appropriate instead of above:
> asm("tlbi       vaae1is, %0" : : "r" (addr));

You should use the vaae1is variant for all ASIDs since it's a global
mapping (see flush_tlb_kernel_range()).

-- 
Catalin

[PATCH 1/1] arm64: TLB maintainance: Implement flush_kern_tlb_page

[Ritesh Harjani]

On Mon, May 19, 2014 at 4:31 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Mon, May 19, 2014 at 11:54:31AM +0100, Ritesh Harjani wrote:
>> On Mon, May 19, 2014 at 4:16 PM, Catalin Marinas
>> <catalin.marinas@arm.com> wrote:
>> > On Mon, May 19, 2014 at 11:34:25AM +0100, ritesh.harjani at gmail.com wrote:
>> >> From: Ritesh Harjani <ritesh.harjani@gmail.com>
>> >>
>> >> Implement flush_kern_tlb_page mentioned in the header
>> >> comment of arch/arm64/include/asm/tlbflush.h
>> >
>> > Alternatively, clean-up the comment.
>>
>> You mean this function is of no use ? Or there are other plans which
>> might require clean up of this file ?
>
> Since we don't have it and the kernel builds fine, I guess we don't need
> it.
Ok.

>
>> Also, could you please confirm whether the implementation of the
>> function is correct ?
>>
>> >> +       asm("tlbi       vae1is, %0" : : "r" (addr));
>>
>> Should following instruction be more appropriate instead of above:
>> asm("tlbi       vaae1is, %0" : : "r" (addr));
>
> You should use the vaae1is variant for all ASIDs since it's a global
> mapping (see flush_tlb_kernel_range()).

Yes!!, ok thanks!!.

>
> --
> Catalin


Thanks
Ritesh