From mboxrd@z Thu Jan 1 00:00:00 1970 From: daniel.lezcano@linaro.org (Daniel Lezcano) Date: Fri, 23 May 2014 12:31:39 +0200 Subject: [PATCH 59/71] ARM: sun6i: a31: Add support for the High Speed Timers In-Reply-To: <1400841111-6683-1-git-send-email-daniel.lezcano@linaro.org> References: <537F214C.8000700@linaro.org> <1400841111-6683-1-git-send-email-daniel.lezcano@linaro.org> Message-ID: <1400841111-6683-59-git-send-email-daniel.lezcano@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Maxime Ripard The Allwinner A31 has support for four high speed timers. Apart for the number of timers (4 vs 2), it's basically the same logic than the high speed timers found in the sun5i chips. Now that we have a driver to support it, we can enable them in the device tree. Signed-off-by: Maxime Ripard Signed-off-by: Daniel Lezcano --- arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa7..8cee8a1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -428,6 +428,17 @@ status = "disabled"; }; + timer at 01c60000 { + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <0 51 4>, + <0 52 4>, + <0 53 4>, + <0 54 4>; + clocks = <&ahb1_gates 19>; + resets = <&ahb1_rst 19>; + }; + spi0: spi at 01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; -- 1.7.9.5