[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
the AVP coprocessor and can also serve as a backup for the ARM Cortex
CPU's local interrupt controller (GIC).

The LIC is subdivided into multiple identical units, each handling 32
possible interrupt sources.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- new patch

 .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
new file mode 100644
index 000000000000..c695ec713740
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
@@ -0,0 +1,19 @@
+NVIDIA Tegra Legacy Interrupt Controller
+
+The legacy interrupt controller is divided into units that serve 32 interrupts
+each. Tegra20 implements four units, whereas Tegra30 and later implement five.
+
+Required properties:
+- compatible: "nvidia,tegra<chip>-ictlr"
+- reg: Physical base address and length of the controller's registers. There
+  should be one entry for each unit.
+
+Example:
+
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra20-ictlr";
+		reg = <0x60004000 0x40   /* primary controller */
+		       0x60004100 0x40   /* secondary controller */
+		       0x60004200 0x40   /* tertiary controller */
+		       0x60004300 0x40>; /* quaternary controller */
+	};
-- 
2.0.0

[PATCH v2 2/4] ARM: tegra: Add legacy interrupt controller nodes

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add device tree nodes for the legacy interrupt controller so that the
driver can get the register ranges from device tree rather than hard-
coding them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add chip-specific compatible string
- drop quinary controller on Tegra20

 arch/arm/boot/dts/tegra114.dtsi | 9 +++++++++
 arch/arm/boot/dts/tegra124.dtsi | 9 +++++++++
 arch/arm/boot/dts/tegra20.dtsi  | 8 ++++++++
 arch/arm/boot/dts/tegra30.dtsi  | 9 +++++++++
 4 files changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 335a1d8047f2..88cee16cb4dd 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -138,6 +138,15 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
+		reg = <0x60004000 0x40   /* primary controller */
+		       0x60004100 0x40   /* secondary controller */
+		       0x60004200 0x40   /* tertiary controller */
+		       0x60004300 0x40   /* quaternary controller */
+		       0x60004400 0x40>; /* quinary controller */
+	};
+
 	timer at 60005000 {
 		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index d675186d8eba..71d5f98bdc95 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -102,6 +102,15 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	interrupt-controller at 0,60004000 {
+		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
+		reg = <0x0 0x60004000 0x0 0x40   /* primary controller */
+		       0x0 0x60004100 0x0 0x40   /* secondary controller */
+		       0x0 0x60004200 0x0 0x40   /* tertiary controller */
+		       0x0 0x60004300 0x0 0x40   /* quaternary controller */
+		       0x0 0x60004400 0x0 0x40>; /* quinary controller */
+	};
+
 	timer at 0,60005000 {
 		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 		reg = <0x0 0x60005000 0x0 0x400>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 243d84cdbae8..542ffbea99d1 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -173,6 +173,14 @@
 		cache-level = <2>;
 	};
 
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra20-ictlr";
+		reg = <0x60004000 0x40   /* primary controller */
+		       0x60004100 0x40   /* secondary controller */
+		       0x60004200 0x40   /* tertiary controller */
+		       0x60004300 0x40>; /* quaternary controller */
+	};
+
 	timer at 60005000 {
 		compatible = "nvidia,tegra20-timer";
 		reg = <0x60005000 0x60>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 0b1ede940d1f..2ead5745c712 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -253,6 +253,15 @@
 		cache-level = <2>;
 	};
 
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra30-ictlr";
+		reg = <0x60004000 0x40   /* primary controller */
+		       0x60004100 0x40   /* secondary controller */
+		       0x60004200 0x40   /* tertiary controller */
+		       0x60004300 0x40   /* quaternary controller */
+		       0x60004400 0x40>; /* quinary controller */
+	};
+
 	timer at 60005000 {
 		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
-- 
2.0.0

[PATCH v2 3/4] soc/tegra: Initialize interrupt controller from DT

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Obtains the register ranges for the legacy interrupt controller from DT
and provide hard-coded values as fallback.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- check for the exact number of controllers expected
- fallback to tegra_chip_id for non-DT
- warn on parsing errors

 arch/arm/mach-tegra/iomap.h |  18 -------
 arch/arm/mach-tegra/irq.c   | 123 ++++++++++++++++++++++++++++++++++++--------
 2 files changed, 101 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808e93a3..52bbb5c8fe84 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -28,24 +28,6 @@
 #define TEGRA_ARM_PERIF_BASE		0x50040000
 #define TEGRA_ARM_PERIF_SIZE		SZ_8K
 
-#define TEGRA_ARM_INT_DIST_BASE		0x50041000
-#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
-
-#define TEGRA_PRIMARY_ICTLR_BASE	0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE	0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE	0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE	0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE	SZ_64
-
 #define TEGRA_TMR1_BASE			0x60005000
 #define TEGRA_TMR1_SIZE			SZ_8
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1a74d562dca1..1d52fe961d2b 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -26,9 +26,7 @@
 #include <linux/of_address.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/syscore_ops.h>
-
-#include "board.h"
-#include "iomap.h"
+#include <linux/tegra-soc.h>
 
 #define ICTLR_CPU_IEP_VFIQ	0x08
 #define ICTLR_CPU_IEP_FIR	0x14
@@ -52,13 +50,7 @@
 
 static int num_ictlrs;
 
-static void __iomem *ictlr_reg_base[] = {
-	IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
+static void __iomem *ictlr_reg_base[] = { NULL, NULL, NULL, NULL, NULL };
 
 #ifdef CONFIG_PM_SLEEP
 static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
@@ -70,10 +62,11 @@ static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
 static void __iomem *tegra_gic_cpu_base;
 #endif
 
+static void __iomem *distbase;
+
 bool tegra_pending_sgi(void)
 {
 	u32 pending_set;
-	void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
 
 	pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);
 
@@ -255,24 +248,109 @@ static void tegra114_gic_cpu_pm_registration(void)
 static void tegra114_gic_cpu_pm_registration(void) { }
 #endif
 
+static struct resource ictlr_regs[] = {
+	{ .start = 0x60004000, .end = 0x6000403f, .flags = IORESOURCE_MEM },
+	{ .start = 0x60004100, .end = 0x6000413f, .flags = IORESOURCE_MEM },
+	{ .start = 0x60004200, .end = 0x6000423f, .flags = IORESOURCE_MEM },
+	{ .start = 0x60004300, .end = 0x6000433f, .flags = IORESOURCE_MEM },
+	{ .start = 0x60004400, .end = 0x6000443f, .flags = IORESOURCE_MEM },
+};
+
+struct tegra_ictlr_soc {
+	unsigned int num_ictlrs;
+};
+
+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
+	.num_ictlrs = 4,
+};
+
+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
+	.num_ictlrs = 5,
+};
+
+static const struct of_device_id ictlr_matches[] = {
+	{ .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
+	{ .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
+	{ }
+};
+
+static const struct of_device_id gic_matches[] = {
+	{ .compatible = "arm,cortex-a15-gic", },
+	{ .compatible = "arm,cortex-a9-gic", },
+	{ }
+};
+
 void __init tegra_init_irq(void)
 {
-	int i;
-	void __iomem *distbase;
+	unsigned int max_ictlrs = ARRAY_SIZE(ictlr_regs), i;
+	const struct of_device_id *match;
+	struct device_node *np;
+	struct resource res;
+
+	np = of_find_matching_node_and_match(NULL, ictlr_matches, &match);
+	if (np) {
+		const struct tegra_ictlr_soc *soc = match->data;
+
+		for (i = 0; i < soc->num_ictlrs; i++) {
+			if (of_address_to_resource(np, i, &res) < 0)
+				break;
+
+			ictlr_regs[i] = res;
+		}
+
+		WARN(i != soc->num_ictlrs,
+		     "Found %u interrupt controllers in DT; expected %u.\n",
+		     i, soc->num_ictlrs);
+
+		max_ictlrs = soc->num_ictlrs;
+		of_node_put(np);
+	} else {
+		/*
+		 * If no matching device node was found, fall back to using
+		 * the chip ID.
+		 */
+
+		/* Tegra30 and later have five interrupt controllers, ... */
+		max_ictlrs = ARRAY_SIZE(ictlr_regs);
+
+		/* ..., but Tegra20 only has four. */
+		if (tegra_chip_id <= TEGRA20)
+			max_ictlrs--;
+	}
+
+	np = of_find_matching_node(NULL, gic_matches);
+	if (np) {
+		if (of_address_to_resource(np, 0, &res) < 0) {
+			WARN(1, "GIC registers are missing from DT\n");
+			res.start = res.end = 0;
+		}
 
-	distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
+		of_node_put(np);
+	}
+
+	if (res.start == 0 || res.end == 0) {
+		res.start = 0x50041000;
+		res.end = 0x50041fff;
+		res.flags = IORESOURCE_MEM;
+	}
+
+	distbase = ioremap_nocache(res.start, resource_size(&res));
 	num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
 
-	if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
-		WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
-			num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
-		num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
+	if (num_ictlrs != max_ictlrs) {
+		WARN(1, "Too many (%d) interrupt controllers found. Maximum is %u.",
+		     num_ictlrs, max_ictlrs);
+		num_ictlrs = max_ictlrs;
 	}
 
 	for (i = 0; i < num_ictlrs; i++) {
-		void __iomem *ictlr = ictlr_reg_base[i];
+		struct resource *regs = &ictlr_regs[i];
+		void __iomem *ictlr;
+
+		ictlr = ioremap_nocache(regs->start, resource_size(regs));
 		writel(~0, ictlr + ICTLR_CPU_IER_CLR);
 		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+		ictlr_reg_base[i] = ictlr;
 	}
 
 	gic_arch_extn.irq_ack = tegra_ack;
@@ -287,9 +365,10 @@ void __init tegra_init_irq(void)
 	 * Check if there is a devicetree present, since the GIC will be
 	 * initialized elsewhere under DT.
 	 */
-	if (!of_have_populated_dt())
-		gic_init(0, 29, distbase,
-			IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+	if (!of_have_populated_dt()) {
+		void __iomem *cpubase = ioremap_nocache(0x50040000, 0x2000);
+		gic_init(0, 29, distbase, cpubase);
+	}
 
 	tegra114_gic_cpu_pm_registration();
 }
-- 
2.0.0

[PATCH v2 4/4] soc/tegra: Remove unused defines

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Eventually the aim is to get rid of this file because it cannot be built
on ARM64. Until it can be completely removed, eliminate unused entries
to make it easier to see which are still used.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/mach-tegra/iomap.h | 30 ------------------------------
 1 file changed, 30 deletions(-)

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 52bbb5c8fe84..c2fd86a9b43f 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -28,21 +28,9 @@
 #define TEGRA_ARM_PERIF_BASE		0x50040000
 #define TEGRA_ARM_PERIF_SIZE		SZ_8K
 
-#define TEGRA_TMR1_BASE			0x60005000
-#define TEGRA_TMR1_SIZE			SZ_8
-
-#define TEGRA_TMR2_BASE			0x60005008
-#define TEGRA_TMR2_SIZE			SZ_8
-
 #define TEGRA_TMRUS_BASE		0x60005010
 #define TEGRA_TMRUS_SIZE		SZ_64
 
-#define TEGRA_TMR3_BASE			0x60005050
-#define TEGRA_TMR3_SIZE			SZ_8
-
-#define TEGRA_TMR4_BASE			0x60005058
-#define TEGRA_TMR4_SIZE			SZ_8
-
 #define TEGRA_CLK_RESET_BASE		0x60006000
 #define TEGRA_CLK_RESET_SIZE		SZ_4K
 
@@ -58,21 +46,6 @@
 #define TEGRA_APB_MISC_BASE		0x70000000
 #define TEGRA_APB_MISC_SIZE		SZ_4K
 
-#define TEGRA_UARTA_BASE		0x70006000
-#define TEGRA_UARTA_SIZE		SZ_64
-
-#define TEGRA_UARTB_BASE		0x70006040
-#define TEGRA_UARTB_SIZE		SZ_64
-
-#define TEGRA_UARTC_BASE		0x70006200
-#define TEGRA_UARTC_SIZE		SZ_256
-
-#define TEGRA_UARTD_BASE		0x70006300
-#define TEGRA_UARTD_SIZE		SZ_256
-
-#define TEGRA_UARTE_BASE		0x70006400
-#define TEGRA_UARTE_SIZE		SZ_256
-
 #define TEGRA_PMC_BASE			0x7000E400
 #define TEGRA_PMC_SIZE			SZ_256
 
@@ -91,9 +64,6 @@
 #define TEGRA124_EMC_BASE		0x7001B000
 #define TEGRA124_EMC_SIZE		SZ_2K
 
-#define TEGRA_CSITE_BASE		0x70040000
-#define TEGRA_CSITE_SIZE		SZ_256K
-
 /* On TEGRA, many peripherals are very closely packed in
  * two 256MB io windows (that actually only use about 64KB
  * at the start of each).
-- 
2.0.0

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Mark Rutland]

On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
> the AVP coprocessor and can also serve as a backup for the ARM Cortex
> CPU's local interrupt controller (GIC).
> 
> The LIC is subdivided into multiple identical units, each handling 32
> possible interrupt sources.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - new patch
> 
>  .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
> new file mode 100644
> index 000000000000..c695ec713740
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
> @@ -0,0 +1,19 @@
> +NVIDIA Tegra Legacy Interrupt Controller
> +
> +The legacy interrupt controller is divided into units that serve 32 interrupts
> +each. Tegra20 implements four units, whereas Tegra30 and later implement five.
> +
> +Required properties:
> +- compatible: "nvidia,tegra<chip>-ictlr"

And valid <chip> values are?

> +- reg: Physical base address and length of the controller's registers. There
> +  should be one entry for each unit.
> +
> +Example:
> +
> +	interrupt-controller at 60004000 {
> +		compatible = "nvidia,tegra20-ictlr";
> +		reg = <0x60004000 0x40   /* primary controller */
> +		       0x60004100 0x40   /* secondary controller */
> +		       0x60004200 0x40   /* tertiary controller */
> +		       0x60004300 0x40>; /* quaternary controller */

Could we please bracket the entries individually, e.g.

		reg = <0x60004000 0x40>,
		      <0x60004100 0x40>,
		      <0x60004200 0x40>,
		      <0x60004300 0x40>;

How do the interrupt lines correspond to those of the GIC?

Cheers,
Mark.

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Stephen Warren]

On 06/30/2014 11:43 AM, Mark Rutland wrote:
> On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
>> the AVP coprocessor and can also serve as a backup for the ARM Cortex
>> CPU's local interrupt controller (GIC).
>>
>> The LIC is subdivided into multiple identical units, each handling 32
>> possible interrupt sources.
>>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> Changes in v2:
>> - new patch
>>
>>  .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>> new file mode 100644
>> index 000000000000..c695ec713740
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
>> @@ -0,0 +1,19 @@
>> +NVIDIA Tegra Legacy Interrupt Controller
>> +
>> +The legacy interrupt controller is divided into units that serve 32 interrupts
>> +each. Tegra20 implements four units, whereas Tegra30 and later implement five.
>> +
>> +Required properties:
>> +- compatible: "nvidia,tegra<chip>-ictlr"
> 
> And valid <chip> values are?

Do you really want us to edit every single binding every time a new chip
comes out? Surely just relying NVIDIA's published chip names is fine?

[PATCH v2 3/4] soc/tegra: Initialize interrupt controller from DT

[Stephen Warren]

On 06/27/2014 07:02 PM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Obtains the register ranges for the legacy interrupt controller from DT
> and provide hard-coded values as fallback.

> diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
> -	if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
> -		WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
> -			num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
> -		num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
> +	if (num_ictlrs != max_ictlrs) {
> +		WARN(1, "Too many (%d) interrupt controllers found. Maximum is %u.",
> +		     num_ictlrs, max_ictlrs);

We should change that message to something more like:

Wrong number (%d) interrupt controllers found. Expected %u.

Feel free to make that a separate patch though.

> -	if (!of_have_populated_dt())
> -		gic_init(0, 29, distbase,
> -			IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
> +	if (!of_have_populated_dt()) {
> +		void __iomem *cpubase = ioremap_nocache(0x50040000, 0x2000);
> +		gic_init(0, 29, distbase, cpubase);
> +	}

That if will never fire these days. We should rip out that block sometime.

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Stephen Warren]

On 06/27/2014 07:02 PM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
> the AVP coprocessor and can also serve as a backup for the ARM Cortex
> CPU's local interrupt controller (GIC).
> 
> The LIC is subdivided into multiple identical units, each handling 32
> possible interrupt sources.

The series looks OK to me, although I guess there will be a V3 to
address Mark's comments?

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Mark Rutland]

On Mon, Jun 30, 2014 at 07:38:13PM +0100, Stephen Warren wrote:
> On 06/30/2014 11:43 AM, Mark Rutland wrote:
> > On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote:
> >> From: Thierry Reding <treding@nvidia.com>
> >>
> >> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
> >> the AVP coprocessor and can also serve as a backup for the ARM Cortex
> >> CPU's local interrupt controller (GIC).
> >>
> >> The LIC is subdivided into multiple identical units, each handling 32
> >> possible interrupt sources.
> >>
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >> Changes in v2:
> >> - new patch
> >>
> >>  .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
> >>  1 file changed, 19 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
> >> new file mode 100644
> >> index 000000000000..c695ec713740
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
> >> @@ -0,0 +1,19 @@
> >> +NVIDIA Tegra Legacy Interrupt Controller
> >> +
> >> +The legacy interrupt controller is divided into units that serve 32 interrupts
> >> +each. Tegra20 implements four units, whereas Tegra30 and later implement five.
> >> +
> >> +Required properties:
> >> +- compatible: "nvidia,tegra<chip>-ictlr"
> > 
> > And valid <chip> values are?
> 
> Do you really want us to edit every single binding every time a new chip
> comes out? Surely just relying NVIDIA's published chip names is fine?
> 

While I am not a fan of wildcards in documentation, if you feel this is
clear as is then feel free to leave it as-is. The example is probably
sufficient.

Mark.

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Stephen Warren]

On 06/30/2014 02:32 PM, Stephen Warren wrote:
> On 06/27/2014 07:02 PM, Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
>> the AVP coprocessor and can also serve as a backup for the ARM Cortex
>> CPU's local interrupt controller (GIC).
>>
>> The LIC is subdivided into multiple identical units, each handling 32
>> possible interrupt sources.
>
> The series looks OK to me, although I guess there will be a V3 to
> address Mark's comments?

Thierry, do you still want this series applied? I'm not sure if it's 
required by or conflicts with any of your later patches to move code out 
of arch/arm/mach-tegra/?

If this series should still be applied, I guess I can fix up Mark's 
remaining comment (the bracketing of the multiple reg entries in the DT) 
when applying it, at least if you don't want to repost it yourself.

[PATCH v2 1/4] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Thierry Reding]

On Mon, Aug 25, 2014 at 11:35:42AM -0600, Stephen Warren wrote:
> On 06/30/2014 02:32 PM, Stephen Warren wrote:
> >On 06/27/2014 07:02 PM, Thierry Reding wrote:
> >>From: Thierry Reding <treding@nvidia.com>
> >>
> >>The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
> >>the AVP coprocessor and can also serve as a backup for the ARM Cortex
> >>CPU's local interrupt controller (GIC).
> >>
> >>The LIC is subdivided into multiple identical units, each handling 32
> >>possible interrupt sources.
> >
> >The series looks OK to me, although I guess there will be a V3 to
> >address Mark's comments?
> 
> Thierry, do you still want this series applied? I'm not sure if it's
> required by or conflicts with any of your later patches to move code out of
> arch/arm/mach-tegra/?
> 
> If this series should still be applied, I guess I can fix up Mark's
> remaining comment (the bracketing of the multiple reg entries in the DT)
> when applying it, at least if you don't want to repost it yourself.

This was originally meant to be moved out of arch/arm/mach-tegra and
shared for upcoming 64-bit SoCs, but it seems like we may not need this
code for 64-bit at all.

On the other hand the series is an improvement over what we've had
before, so there may still be some value in merging it. I'll respin v3.

Thierry
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