From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 06/12] soc/tegra: Add efuse and apbmisc bindings
Date: Fri, 11 Jul 2014 14:16:05 +0200 [thread overview]
Message-ID: <1405080971-7609-7-git-send-email-thierry.reding@gmail.com> (raw)
In-Reply-To: <1405080971-7609-1-git-send-email-thierry.reding@gmail.com>
From: Peter De Schrijver <pdeschrijver@nvidia.com>
Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and
Tegra124.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/fuse/nvidia,tegra20-fuse.txt | 40 ++++++++++++++++++++++
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 13 +++++++
arch/arm/boot/dts/tegra114.dtsi | 15 ++++++++
arch/arm/boot/dts/tegra124.dtsi | 15 ++++++++
arch/arm/boot/dts/tegra20.dtsi | 15 ++++++++
arch/arm/boot/dts/tegra30.dtsi | 15 ++++++++
6 files changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
new file mode 100644
index 000000000000..d8c98c7614d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
@@ -0,0 +1,40 @@
+NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
+
+Required properties:
+- compatible : should be:
+ "nvidia,tegra20-efuse"
+ "nvidia,tegra30-efuse"
+ "nvidia,tegra114-efuse"
+ "nvidia,tegra124-efuse"
+ Details:
+ nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
+ due to a hardware bug. Tegra20 also lacks certain information which is
+ available in later generations such as fab code, lot code, wafer id,..
+ nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
+ The differences between these SoCs are the size of the efuse array,
+ the location of the spare (OEM programmable) bits and the location of
+ the speedo data.
+- reg: Should contain 1 entry: the entry gives the physical address and length
+ of the fuse registers.
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - fuse
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - fuse
+
+Example:
+
+ fuse at 7000f800 {
+ compatible = "nvidia,tegra20-efuse";
+ reg = <0x7000F800 0x400>,
+ <0x70000000 0x400>;
+ clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
+
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
new file mode 100644
index 000000000000..b97b8bef1fe5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -0,0 +1,13 @@
+NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
+
+Required properties:
+- compatible : should be:
+ "nvidia,tegra20-apbmisc"
+ "nvidia,tegra30-apbmisc"
+ "nvidia,tegra114-apbmisc"
+ "nvidia,tegra124-apbmisc"
+- reg: Should contain 2 entries: the first entry gives the physical address
+ and length of the registers which contain revision and debug features.
+ The second entry gives the physical address and length of the
+ registers indicating the strapping options.
+
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index fdc559ab2db3..335a1d8047f2 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -220,6 +220,12 @@
interrupt-controller;
};
+ apbmisc at 70000800 {
+ compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64 /* Chip revision */
+ 0x70000008 0x04>; /* Strapping options */
+ };
+
pinmux: pinmux at 70000868 {
compatible = "nvidia,tegra114-pinmux";
reg = <0x70000868 0x148 /* Pad control registers */
@@ -485,6 +491,15 @@
clock-names = "pclk", "clk32k_in";
};
+ fuse@7000f800 {
+ compatible = "nvidia,tegra114-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA114_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
iommu at 70019010 {
compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
reg = <0x70019010 0x02c
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 6e6bc4e8185c..226941c07d15 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -179,6 +179,12 @@
#dma-cells = <1>;
};
+ apbmisc at 0,70000800 {
+ compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
+ reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
+ <0x0 0x7000E864 0x0 0x04>; /* Strapping options */
+ };
+
pinmux: pinmux at 0,70000868 {
compatible = "nvidia,tegra124-pinmux";
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
@@ -449,6 +455,15 @@
clock-names = "pclk", "clk32k_in";
};
+ fuse at 0,7000f800 {
+ compatible = "nvidia,tegra124-efuse";
+ reg = <0x0 0x7000f800 0x0 0x400>;
+ clocks = <&tegra_car TEGRA124_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
sdhci at 0,700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index a7ddf70df50b..243d84cdbae8 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -236,6 +236,12 @@
interrupt-controller;
};
+ apbmisc at 70000800 {
+ compatible = "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64 /* Chip revision */
+ 0x70000008 0x04>; /* Strapping options */
+ };
+
pinmux: pinmux at 70000014 {
compatible = "nvidia,tegra20-pinmux";
reg = <0x70000014 0x10 /* Tri-state registers */
@@ -545,6 +551,15 @@
#size-cells = <0>;
};
+ fuse at 7000f800 {
+ compatible = "nvidia,tegra20-efuse";
+ reg = <0x7000F800 0x400>;
+ clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
pcie-controller at 80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dec4fc823901..0b1ede940d1f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -335,6 +335,12 @@
interrupt-controller;
};
+ apbmisc at 70000800 {
+ compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64 /* Chip revision */
+ 0x70000008 0x04>; /* Strapping options */
+ };
+
pinmux: pinmux at 70000868 {
compatible = "nvidia,tegra30-pinmux";
reg = <0x70000868 0xd4 /* Pad control registers */
@@ -631,6 +637,15 @@
nvidia,ahb = <&ahb>;
};
+ fuse at 7000f800 {
+ compatible = "nvidia,tegra30-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA30_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
ahub at 70080000 {
compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200
--
2.0.1
next prev parent reply other threads:[~2014-07-11 12:16 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-11 12:15 [PATCH 00/12] Add NVIDIA Tegra FUSE driver Thierry Reding
2014-07-11 12:16 ` [PATCH 01/12] ARM: tegra: Sort includes alphabetically Thierry Reding
2014-07-11 12:16 ` [PATCH 02/12] ARM: tegra: Use a function to get the chip ID Thierry Reding
2014-07-11 12:16 ` [PATCH 03/12] ARM: tegra: export apb dma readl/writel Thierry Reding
2014-07-11 12:16 ` [PATCH 04/12] ARM: tegra: move fuse exports to tegra-soc.h Thierry Reding
2014-07-11 12:16 ` [PATCH 05/12] soc/tegra: Add efuse driver for Tegra Thierry Reding
2014-10-19 3:12 ` Shawn Guo
2014-11-10 15:10 ` Thierry Reding
2014-07-11 12:16 ` Thierry Reding [this message]
2014-07-11 12:16 ` [PATCH 07/12] soc/tegra: fuse: move APB DMA into Tegra20 fuse driver Thierry Reding
2014-07-11 12:16 ` [PATCH 08/12] misc: fuse: fix dummy functions Thierry Reding
2014-07-11 12:16 ` [PATCH 09/12] ARM: tegra: Setup CPU hotplug in a pure initcall Thierry Reding
2014-07-11 12:16 ` [PATCH 10/12] ARM: tegra: Always lock the CPU reset vector Thierry Reding
2014-07-11 12:16 ` [PATCH 11/12] soc/tegra: fuse: Set up in early initcall Thierry Reding
2014-07-11 12:16 ` [PATCH 12/12] ARM: tegra: Convert PMC to a driver Thierry Reding
2014-07-11 13:58 ` Peter De Schrijver
2014-07-14 8:06 ` Thierry Reding
2014-07-16 11:56 ` Arnd Bergmann
2014-07-16 13:22 ` Thierry Reding
2014-07-16 14:12 ` Arnd Bergmann
2014-07-16 15:14 ` Thierry Reding
2014-07-16 15:22 ` Arnd Bergmann
2014-07-16 18:57 ` Thierry Reding
2014-07-16 19:34 ` Olof Johansson
2014-07-17 8:54 ` Arnd Bergmann
2014-07-17 11:06 ` Thierry Reding
2014-07-21 12:06 ` Arnd Bergmann
2014-07-21 13:12 ` Thierry Reding
2014-07-21 13:16 ` Tejun Heo
2014-07-21 13:39 ` Thierry Reding
2014-07-17 8:53 ` Peter De Schrijver
2014-07-17 9:01 ` Peter De Schrijver
2014-07-17 11:01 ` Thierry Reding
2014-07-21 7:09 ` Vince Hsu
2014-07-21 9:02 ` Thierry Reding
2014-07-22 3:34 ` Vince Hsu
2014-07-13 6:38 ` [PATCH 00/12] Add NVIDIA Tegra FUSE driver Olof Johansson
2014-07-14 6:57 ` Thierry Reding
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