From: jingchang.lu@freescale.com (Jingchang Lu)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND 1/2] dt-binding: fsl-lpuart: use exact SoC revision to document binding
Date: Mon, 14 Jul 2014 17:41:10 +0800 [thread overview]
Message-ID: <1405330871-9038-2-git-send-email-jingchang.lu@freescale.com> (raw)
In-Reply-To: <1405330871-9038-1-git-send-email-jingchang.lu@freescale.com>
use exact SoC revision instead of wildcard describing
to make the binding more clearer.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
index a1d1205..c95005e 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
@@ -1,7 +1,11 @@
* Freescale low power universal asynchronous receiver/transmitter (lpuart)
Required properties:
-- compatible : Should be "fsl,<soc>-lpuart"
+- compatible :
+ - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
+ on Vybrid vf610 SoC with 8-bit register organization
+ - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
+ on LS1021A SoC with 32-bit big-endian register organization
- reg : Address and length of the register set for the device
- interrupts : Should contain uart interrupt
- clocks : phandle + clock specifier pairs, one for each entry in clock-names
--
1.8.0
next prev parent reply other threads:[~2014-07-14 9:41 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-14 9:41 [PATCHv2 0/2] tty: serial: fsl_lpuart: add 32-bit register support and dt-binding Jingchang Lu
2014-07-14 9:41 ` Jingchang Lu [this message]
2014-07-14 9:41 ` [PATCHv2 2/2] tty: serial: fsl_lpuart: add 32-bit register interface support Jingchang Lu
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