[PATCH v2 0/5] ARM: dts: sun6i: Add support for GMAC

[PATCH v2 0/5] ARM: dts: sun6i: Add support for GMAC

[Chen-Yu Tsai]

Hi Maxime,

This is v2 of the A31 GMAC support series. The GMAC is the same as in
the A20, except it has an extra reset control. The GMAC clock module is
mostly the same as in the A20, without the extra dividers, which I left
out intentionally from the clock driver.

The register offsets and interrupts were copied from A31 SDK in Rhombus
Tech's repository. The pin muxes were from the EVB fex file.

I've tested this on my A31 Hummingbird under 100M and 1000M.

Patch 5 adds support for the A31 Hummingbird. It is based on your work,
so it has your name on it. I cleaned up the format and descriptions,
got rid of missing devices, and added usb and the external rtc. 


Changes since v1:

- Dropped Colombus board patch, as it needs AXP221 regulator support.
- Added reset-name to GMAC node.
- Added A31 Hummingbird support.


Cheers,
ChenYu

Chen-Yu Tsai (4):
  ARM: dts: sun6i: Add pin muxing options for GMAC
  ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi
  ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node
  ARM: dts: sun6i: Add ethernet alias for GMAC

Maxime Ripard (1):
  ARM: dts: sun6i: Add Merrii A31 Hummingbird support

 arch/arm/boot/dts/Makefile                  |   1 +
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 119 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/sun6i-a31.dtsi            |  88 ++++++++++++++++++++
 3 files changed, 208 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun6i-a31-hummingbird.dts

-- 
2.0.1

[PATCH v2 1/5] ARM: dts: sun6i: Add pin muxing options for GMAC

[Chen-Yu Tsai]

The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index baf8eff..47e143a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -467,6 +467,48 @@
 				allwinner,drive = <2>;
 				allwinner,pull = <0>;
 			};
+
+			gmac_pins_mii_a: gmac_mii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA8", "PA9", "PA11",
+						"PA12", "PA13", "PA14", "PA19",
+						"PA20", "PA21", "PA22", "PA23",
+						"PA24", "PA26", "PA27";
+				allwinner,function = "gmac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_gmii_a: gmac_gmii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA4", "PA5", "PA6", "PA7",
+						"PA8", "PA9", "PA10", "PA11",
+						"PA12", "PA13", "PA14",	"PA15",
+						"PA16", "PA17", "PA18", "PA19",
+						"PA20", "PA21", "PA22", "PA23",
+						"PA24", "PA25", "PA26", "PA27";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in GMII mode run at 125MHz and
+				 * might need a higher signal drive strength
+				 */
+				allwinner,drive = <2>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_rgmii_a: gmac_rgmii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA9", "PA10", "PA11",
+						"PA12", "PA13", "PA14", "PA19",
+						"PA20", "PA25", "PA26", "PA27";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in RGMII mode use DDR mode
+				 * and need a higher signal drive strength
+				 */
+				allwinner,drive = <3>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		ahb1_rst: reset at 01c202c0 {
-- 
2.0.1

[PATCH v2 2/5] ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi

[Chen-Yu Tsai]

The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 47e143a..b78a5aa 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -281,6 +281,34 @@
 					     "usb_ohci0", "usb_ohci1",
 					     "usb_ohci2";
 		};
+
+		/*
+		 * The following two are dummy clocks, placeholders used in the gmac_tx
+		 * clock. The gmac driver will choose one parent depending on the PHY
+		 * interface mode, using clk_set_rate auto-reparenting.
+		 * The actual TX clock rate is not controlled by the gmac_tx clock.
+		 */
+		mii_phy_tx_clk: clk at 1 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+			clock-output-names = "mii_phy_tx";
+		};
+
+		gmac_int_tx_clk: clk at 2 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+			clock-output-names = "gmac_int_tx";
+		};
+
+		gmac_tx_clk: clk at 01c200d0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-gmac-clk";
+			reg = <0x01c200d0 0x4>;
+			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+			clock-output-names = "gmac_tx";
+		};
 	};
 
 	soc at 01c00000 {
-- 
2.0.1

[PATCH v2 3/5] ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node

[Chen-Yu Tsai]

The A31 has the same GMAC found on the A20 SoC, except it has
an extra reset control.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b78a5aa..578fde2 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -691,6 +691,23 @@
 			status = "disabled";
 		};
 
+		gmac: ethernet at 01c30000 {
+			compatible = "allwinner,sun7i-a20-gmac";
+			reg = <0x01c30000 0x1054>;
+			interrupts = <0 82 4>;
+			interrupt-names = "macirq";
+			clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			resets = <&ahb1_rst 17>;
+			reset-names = "stmmaceth";
+			snps,pbl = <2>;
+			snps,fixed-burst;
+			snps,force_sf_dma_mode;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		timer at 01c60000 {
 			compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 			reg = <0x01c60000 0x1000>;
-- 
2.0.1

[PATCH v2 4/5] ARM: dts: sun6i: Add ethernet alias for GMAC

[Chen-Yu Tsai]

Alias GMAC as ethernet0 so U-boot can fill in the MAC address.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 578fde2..44b07e5 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -23,6 +23,7 @@
 		serial3 = &uart3;
 		serial4 = &uart4;
 		serial5 = &uart5;
+		ethernet0 = &gmac;
 	};
 
 
-- 
2.0.1

[PATCH v2 5/5] ARM: dts: sun6i: Add Merrii A31 Hummingbird support

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

This adds support for the A31 Hummingbird:
http://www.merrii.com/en/pla_d.asp?id=172

The Merrii A31 Hummingbird is a development board based on the
Allwinner A31 SoC with multiple USB ports through a USB hub chip,
a uSD slot, a 10/100/1000M ethernet port, an AP6210 WiFi/BT chip,
TV-in, HDMI, VGA, audio in/out ports, and LCD/CSI headers.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens at csie.org: enable usbphy, ehci0, ohci0 for on-board usb hub;
 add pcf8563 rtc node; add comments for i2c0 and mmc0 pull-ups;
 correct ethernet phy address to 0x01; drop uart2 (BT chip has
 no power) and uart3 (no device); use proper commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/Makefile                  |   1 +
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 119 ++++++++++++++++++++++++++++
 2 files changed, 120 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun6i-a31-hummingbird.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c3ee9fb..8be3687 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -375,6 +375,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
 dtb-$(CONFIG_MACH_SUN6I) += \
 	sun6i-a31-app4-evb1.dtb \
 	sun6i-a31-colombus.dtb \
+	sun6i-a31-hummingbird.dtb \
 	sun6i-a31-m9.dtb
 dtb-$(CONFIG_MACH_SUN7I) += \
 	sun7i-a20-cubieboard2.dtb \
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
new file mode 100644
index 0000000..f142065
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun6i-a31.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+	model = "Merrii A31 Hummingbird";
+	compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31";
+
+	chosen {
+		bootargs = "earlyprintk console=ttyS0,115200";
+	};
+
+	soc at 01c00000 {
+		mmc0: mmc at 01c0f000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
+			vmmc-supply = <&reg_vcc3v0>;
+			bus-width = <4>;
+			cd-gpios = <&pio 0 8 0>; /* PA8 */
+			cd-inverted;
+			status = "okay";
+		};
+
+		usbphy: phy at 01c19400 {
+			usb1_vbus-supply = <&reg_usb1_vbus>;
+			status = "okay";
+		};
+
+		ehci0: usb at 01c1a000 {
+			status = "okay";
+		};
+
+		ohci0: usb at 01c1a400 {
+			status = "okay";
+		};
+
+		pio: pinctrl at 01c20800 {
+			mmc0_pins_a: mmc0 at 0 {
+				/* external pull-ups missing for some pins */
+				allwinner,pull = <1>;
+			};
+
+			mmc0_cd_pin_hummingbird: mmc0_cd_pin at 0 {
+				allwinner,pins = "PA8";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			usb1_vbus_pin_a: usb1_vbus_pin at 0 {
+				allwinner,pins = "PH24";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+
+		uart0: serial at 01c28000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins_a>;
+			status = "okay";
+		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			/* pull-ups and devices require AXP221 DLDO3 */
+			status = "failed";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+
+			pcf8563: rtc at 51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		gmac: ethernet at 01c30000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_rgmii_a>;
+			phy = <&phy1>;
+			phy-mode = "rgmii";
+			status = "okay";
+
+			phy1: ethernet-phy at 1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	reg_usb1_vbus: usb1-vbus {
+		pinctrl-0 = <&usb1_vbus_pin_a>;
+		gpio = <&pio 7 24 0>; /* PH24 */
+		status = "okay";
+	};
+};
-- 
2.0.1

[PATCH v2 0/5] ARM: dts: sun6i: Add support for GMAC

[Maxime Ripard]

Hi,

On Wed, Jul 16, 2014 at 01:15:42AM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
> 
> This is v2 of the A31 GMAC support series. The GMAC is the same as in
> the A20, except it has an extra reset control. The GMAC clock module is
> mostly the same as in the A20, without the extra dividers, which I left
> out intentionally from the clock driver.
> 
> The register offsets and interrupts were copied from A31 SDK in Rhombus
> Tech's repository. The pin muxes were from the EVB fex file.
> 
> I've tested this on my A31 Hummingbird under 100M and 1000M.
> 
> Patch 5 adds support for the A31 Hummingbird. It is based on your work,
> so it has your name on it. I cleaned up the format and descriptions,
> got rid of missing devices, and added usb and the external rtc. 

Applied all the patches. Thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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