From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 10/11] arm64: Clean up the initial page table creation in head.S
Date: Wed, 16 Jul 2014 20:09:51 +0100 [thread overview]
Message-ID: <1405537792-23666-11-git-send-email-catalin.marinas@arm.com> (raw)
In-Reply-To: <1405537792-23666-1-git-send-email-catalin.marinas@arm.com>
This patch adds a create_table_entry macro which is used to populate pgd
and pud entries, also reducing the number of arguments for
create_pgd_entry.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/kernel/head.S | 59 ++++++++++++++++++++++--------------------------
1 file changed, 27 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 019f81d9f1d5..a6db505411bc 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -476,43 +476,38 @@ ENDPROC(__calc_phys_offset)
.quad PAGE_OFFSET
/*
- * Macro to populate the PUD for the corresponding block entry in the next
- * level (tbl) for the given virtual address in case of 4 levels.
+ * Macro to create a table entry to the next page.
*
- * Preserves: pgd, virt
- * Corrupts: tbl, tmp1, tmp2
- * Returns: pud
+ * tbl: page table address
+ * virt: virtual address
+ * shift: #imm page table shift
+ * ptrs: #imm pointers per table page
+ *
+ * Preserves: virt
+ * Corrupts: tmp1, tmp2
+ * Returns: tbl -> next level table page address
*/
- .macro create_pud_entry, pgd, tbl, virt, pud, tmp1, tmp2
-#if CONFIG_ARM64_PGTABLE_LEVELS == 4
- add \tbl, \tbl, #PAGE_SIZE // bump tbl 1 page up.
- // to make room for pud
- add \pud, \pgd, #PAGE_SIZE // pgd points to pud which
- // follows pgd
- lsr \tmp1, \virt, #PUD_SHIFT
- and \tmp1, \tmp1, #PTRS_PER_PUD - 1 // PUD index
- orr \tmp2, \tbl, #3 // PUD entry table type
- str \tmp2, [\pud, \tmp1, lsl #3]
-#else
- mov \pud, \tbl
-#endif
+ .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
+ lsr \tmp1, \virt, #\shift
+ and \tmp1, \tmp1, #\ptrs - 1 // table index
+ add \tmp2, \tbl, #PAGE_SIZE
+ orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
+ str \tmp2, [\tbl, \tmp1, lsl #3]
+ add \tbl, \tbl, #PAGE_SIZE // next level table page
.endm
/*
* Macro to populate the PGD (and possibily PUD) for the corresponding
* block entry in the next level (tbl) for the given virtual address.
*
- * Preserves: pgd, virt
- * Corrupts: tmp1, tmp2, tmp3
- * Returns: tbl -> page where block mappings can be placed
- * (changed to make room for pud with 4 levels, preserved otherwise)
+ * Preserves: tbl, next, virt
+ * Corrupts: tmp1, tmp2
*/
- .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2, tmp3
- create_pud_entry \pgd, \tbl, \virt, \tmp3, \tmp1, \tmp2
- lsr \tmp1, \virt, #PGDIR_SHIFT
- and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
- orr \tmp2, \tmp3, #3 // PGD entry table type
- str \tmp2, [\pgd, \tmp1, lsl #3]
+ .macro create_pgd_entry, tbl, virt, tmp1, tmp2
+ create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
+#if CONFIG_ARM64_PGTABLE_LEVELS == 4
+ create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
+#endif
.endm
/*
@@ -573,10 +568,10 @@ __create_page_tables:
/*
* Create the identity mapping.
*/
- add x0, x25, #PAGE_SIZE // section table address
+ mov x0, x25 // idmap_pg_dir
ldr x3, =KERNEL_START
add x3, x3, x28 // __pa(KERNEL_START)
- create_pgd_entry x25, x0, x3, x1, x5, x6
+ create_pgd_entry x0, x3, x5, x6
ldr x6, =KERNEL_END
mov x5, x3 // __pa(KERNEL_START)
add x6, x6, x28 // __pa(KERNEL_END)
@@ -585,9 +580,9 @@ __create_page_tables:
/*
* Map the kernel image (starting with PHYS_OFFSET).
*/
- add x0, x26, #PAGE_SIZE // section table address
+ mov x0, x26 // swapper_pg_dir
mov x5, #PAGE_OFFSET
- create_pgd_entry x26, x0, x5, x1, x3, x6
+ create_pgd_entry x0, x5, x3, x6
ldr x6, =KERNEL_END
mov x3, x24 // phys offset
create_block_map x0, x7, x3, x5, x6
next prev parent reply other threads:[~2014-07-16 19:09 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-16 19:09 [PATCH v7 00/11] arm64: Support 4 levels of translation tables Catalin Marinas
2014-07-16 19:09 ` [PATCH v7 01/11] arm64: Use pr_* instead of printk Catalin Marinas
2014-07-16 19:09 ` [PATCH v7 02/11] arm64: Remove duplicate (SWAPPER|IDMAP)_DIR_SIZE definitions Catalin Marinas
2014-07-17 10:49 ` Mark Rutland
2014-07-16 19:09 ` [PATCH v7 03/11] arm64: Do not initialise the fixmap page tables in head.S Catalin Marinas
2014-07-16 23:14 ` Geoff Levand
2014-07-16 19:09 ` [PATCH v7 04/11] arm64: Introduce VA_BITS and translation level options Catalin Marinas
2014-07-16 19:09 ` [PATCH v7 05/11] arm64: Add a description on 48-bit address space with 4KB pages Catalin Marinas
2014-07-16 19:09 ` [PATCH v7 06/11] arm64: Add 4 levels of page tables definition " Catalin Marinas
2014-07-16 19:09 ` [PATCH v7 07/11] arm64: mm: Implement 4 levels of translation tables Catalin Marinas
2014-07-28 15:40 ` Joel Schopp
2014-07-16 19:09 ` [PATCH v7 08/11] arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELS Catalin Marinas
2014-07-16 19:09 ` [PATCH v7 09/11] arm64: Remove asm/pgtable-*level-hwdef.h files Catalin Marinas
2014-07-16 19:09 ` Catalin Marinas [this message]
2014-07-16 19:09 ` [PATCH v7 11/11] arm64: Determine the vmalloc/vmemmap space at build time based on VA_BITS Catalin Marinas
2014-07-17 10:15 ` [PATCH v7 00/11] arm64: Support 4 levels of translation tables Will Deacon
2014-07-18 17:12 ` [PATCH 12/11] arm64: Remove asm/pgtable-*level-types.h files Catalin Marinas
2014-07-21 15:09 ` [PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration Catalin Marinas
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