* [PATCH 1/3] arm64: fix typo in I-cache policy detection
@ 2014-08-04 8:16 Ard Biesheuvel
2014-08-04 8:16 ` [PATCH 2/3] arm64: add helper functions to read I-cache attributes Ard Biesheuvel
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ard Biesheuvel @ 2014-08-04 8:16 UTC (permalink / raw)
To: linux-arm-kernel
This removes an unfortunately placed semi-colon resulting in all instruction
caches being classified as AIVIVT.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/kernel/cpuinfo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index f82f7d1c468e..744fad2ff418 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -49,7 +49,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
if (l1ip != ICACHE_POLICY_PIPT)
set_bit(ICACHEF_ALIASING, &__icache_flags);
- if (l1ip == ICACHE_POLICY_AIVIVT);
+ if (l1ip == ICACHE_POLICY_AIVIVT)
set_bit(ICACHEF_AIVIVT, &__icache_flags);
pr_info("Detected %s I-cache on CPU%d", icache_policy_str[l1ip], cpu);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] arm64: add helper functions to read I-cache attributes
2014-08-04 8:16 [PATCH 1/3] arm64: fix typo in I-cache policy detection Ard Biesheuvel
@ 2014-08-04 8:16 ` Ard Biesheuvel
2014-08-04 9:58 ` Mark Rutland
2014-08-04 8:16 ` [PATCH 3/3] arm64: don't flag non-aliasing VIPT I-caches as aliasing Ard Biesheuvel
2014-08-04 9:06 ` [PATCH 1/3] arm64: fix typo in I-cache policy detection Mark Rutland
2 siblings, 1 reply; 6+ messages in thread
From: Ard Biesheuvel @ 2014-08-04 8:16 UTC (permalink / raw)
To: linux-arm-kernel
This adds helper functions and #defines to <asm/cachetype.h> to read the
line size and the number of sets from the level 1 instruction cache.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/include/asm/cachetype.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
index 7a2e0762cb40..c0bf1fc3d6a0 100644
--- a/arch/arm64/include/asm/cachetype.h
+++ b/arch/arm64/include/asm/cachetype.h
@@ -39,6 +39,34 @@
extern unsigned long __icache_flags;
+#define CCSIDR_EL1_LINESIZE_MASK 0x7
+#define CCSIDR_EL1_LINESIZE(x) (x & CCSIDR_EL1_LINESIZE_MASK)
+
+#define CCSIDR_EL1_NUMSETS_SHIFT 13
+#define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT)
+#define CCSIDR_EL1_NUMSETS(x) \
+ ((x & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT)
+
+static inline __attribute_const__ u32 icache_get_ccsidr(void)
+{
+ u32 ccsidr;
+
+ /* Select L1 I-cache and read its size ID register */
+ asm("msr csselr_el1, %x1; isb; mrs %x0, ccsidr_el1"
+ : "=r"(ccsidr) : "r"(0x1));
+ return ccsidr;
+}
+
+static inline int icache_get_linesize(void)
+{
+ return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr());
+}
+
+static inline int icache_get_numsets(void)
+{
+ return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr());
+}
+
/*
* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
* permitted in the I-cache.
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] arm64: add helper functions to read I-cache attributes
2014-08-04 8:16 ` [PATCH 2/3] arm64: add helper functions to read I-cache attributes Ard Biesheuvel
@ 2014-08-04 9:58 ` Mark Rutland
2014-08-04 10:38 ` Ard Biesheuvel
0 siblings, 1 reply; 6+ messages in thread
From: Mark Rutland @ 2014-08-04 9:58 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 04, 2014 at 09:16:55AM +0100, Ard Biesheuvel wrote:
> This adds helper functions and #defines to <asm/cachetype.h> to read the
> line size and the number of sets from the level 1 instruction cache.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> arch/arm64/include/asm/cachetype.h | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
> index 7a2e0762cb40..c0bf1fc3d6a0 100644
> --- a/arch/arm64/include/asm/cachetype.h
> +++ b/arch/arm64/include/asm/cachetype.h
> @@ -39,6 +39,34 @@
>
> extern unsigned long __icache_flags;
>
> +#define CCSIDR_EL1_LINESIZE_MASK 0x7
> +#define CCSIDR_EL1_LINESIZE(x) (x & CCSIDR_EL1_LINESIZE_MASK)
It's probably worth bracketing x in case these get used elsewhere.
> +#define CCSIDR_EL1_NUMSETS_SHIFT 13
> +#define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT)
> +#define CCSIDR_EL1_NUMSETS(x) \
> + ((x & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT)
> +
> +static inline __attribute_const__ u32 icache_get_ccsidr(void)
> +{
> + u32 ccsidr;
> +
> + /* Select L1 I-cache and read its size ID register */
> + asm("msr csselr_el1, %x1; isb; mrs %x0, ccsidr_el1"
> + : "=r"(ccsidr) : "r"(0x1));
Does GCC provide any guarantee about the upper bits in this case?
Can we not make both values u64 rather than forcing the use of x
registers within the asm template?
Thanks,
Mark.
> + return ccsidr;
> +}
> +
> +static inline int icache_get_linesize(void)
> +{
> + return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr());
> +}
> +
> +static inline int icache_get_numsets(void)
> +{
> + return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr());
> +}
> +
> /*
> * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
> * permitted in the I-cache.
> --
> 1.8.3.2
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/3] arm64: add helper functions to read I-cache attributes
2014-08-04 9:58 ` Mark Rutland
@ 2014-08-04 10:38 ` Ard Biesheuvel
0 siblings, 0 replies; 6+ messages in thread
From: Ard Biesheuvel @ 2014-08-04 10:38 UTC (permalink / raw)
To: linux-arm-kernel
On 4 August 2014 11:58, Mark Rutland <mark.rutland@arm.com> wrote:
> On Mon, Aug 04, 2014 at 09:16:55AM +0100, Ard Biesheuvel wrote:
>> This adds helper functions and #defines to <asm/cachetype.h> to read the
>> line size and the number of sets from the level 1 instruction cache.
>>
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> arch/arm64/include/asm/cachetype.h | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
>> index 7a2e0762cb40..c0bf1fc3d6a0 100644
>> --- a/arch/arm64/include/asm/cachetype.h
>> +++ b/arch/arm64/include/asm/cachetype.h
>> @@ -39,6 +39,34 @@
>>
>> extern unsigned long __icache_flags;
>>
>> +#define CCSIDR_EL1_LINESIZE_MASK 0x7
>> +#define CCSIDR_EL1_LINESIZE(x) (x & CCSIDR_EL1_LINESIZE_MASK)
>
> It's probably worth bracketing x in case these get used elsewhere.
>
OK
>> +#define CCSIDR_EL1_NUMSETS_SHIFT 13
>> +#define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT)
>> +#define CCSIDR_EL1_NUMSETS(x) \
>> + ((x & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT)
>> +
>> +static inline __attribute_const__ u32 icache_get_ccsidr(void)
>> +{
>> + u32 ccsidr;
>> +
>> + /* Select L1 I-cache and read its size ID register */
>> + asm("msr csselr_el1, %x1; isb; mrs %x0, ccsidr_el1"
>> + : "=r"(ccsidr) : "r"(0x1));
>
> Does GCC provide any guarantee about the upper bits in this case?
>
> Can we not make both values u64 rather than forcing the use of x
> registers within the asm template?
>
Well, this appears to work fine, but making it explicit u64 seems like
the safest option in any case so I am happy to change that.
--
Ard.
>> + return ccsidr;
>> +}
>> +
>> +static inline int icache_get_linesize(void)
>> +{
>> + return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr());
>> +}
>> +
>> +static inline int icache_get_numsets(void)
>> +{
>> + return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr());
>> +}
>> +
>> /*
>> * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
>> * permitted in the I-cache.
>> --
>> 1.8.3.2
>>
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: don't flag non-aliasing VIPT I-caches as aliasing
2014-08-04 8:16 [PATCH 1/3] arm64: fix typo in I-cache policy detection Ard Biesheuvel
2014-08-04 8:16 ` [PATCH 2/3] arm64: add helper functions to read I-cache attributes Ard Biesheuvel
@ 2014-08-04 8:16 ` Ard Biesheuvel
2014-08-04 9:06 ` [PATCH 1/3] arm64: fix typo in I-cache policy detection Mark Rutland
2 siblings, 0 replies; 6+ messages in thread
From: Ard Biesheuvel @ 2014-08-04 8:16 UTC (permalink / raw)
To: linux-arm-kernel
VIPT caches are non-aliasing if the index is derived from address bits that
are always equal between VA and PA. Classifying these as aliasing results in
unnecessary flushing which may hurt performance.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/kernel/cpuinfo.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 744fad2ff418..b780acc201ad 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -47,7 +47,13 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
unsigned int cpu = smp_processor_id();
u32 l1ip = CTR_L1IP(info->reg_ctr);
- if (l1ip != ICACHE_POLICY_PIPT)
+ /*
+ * VIPT caches are non-aliasing if the VA always equals the PA in all
+ * bit positions that are covered by the index, i.e., if num_sets_shift
+ * is less than or equal to PAGE_SHIFT minus line_size_shift.
+ */
+ if (l1ip != ICACHE_POLICY_PIPT && !(l1ip == ICACHE_POLICY_VIPT &&
+ icache_get_linesize() * icache_get_numsets() <= PAGE_SIZE))
set_bit(ICACHEF_ALIASING, &__icache_flags);
if (l1ip == ICACHE_POLICY_AIVIVT)
set_bit(ICACHEF_AIVIVT, &__icache_flags);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/3] arm64: fix typo in I-cache policy detection
2014-08-04 8:16 [PATCH 1/3] arm64: fix typo in I-cache policy detection Ard Biesheuvel
2014-08-04 8:16 ` [PATCH 2/3] arm64: add helper functions to read I-cache attributes Ard Biesheuvel
2014-08-04 8:16 ` [PATCH 3/3] arm64: don't flag non-aliasing VIPT I-caches as aliasing Ard Biesheuvel
@ 2014-08-04 9:06 ` Mark Rutland
2 siblings, 0 replies; 6+ messages in thread
From: Mark Rutland @ 2014-08-04 9:06 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 04, 2014 at 09:16:54AM +0100, Ard Biesheuvel wrote:
> This removes an unfortunately placed semi-colon resulting in all instruction
> caches being classified as AIVIVT.
Whoops, my bad. That obviously shouldn't have been there:
Acked-by: Mark Rutland <mark.rutland@arm.com>
At least this results in a performance hit rather than completely
erroneous operation.
Mark.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> arch/arm64/kernel/cpuinfo.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index f82f7d1c468e..744fad2ff418 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -49,7 +49,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
>
> if (l1ip != ICACHE_POLICY_PIPT)
> set_bit(ICACHEF_ALIASING, &__icache_flags);
> - if (l1ip == ICACHE_POLICY_AIVIVT);
> + if (l1ip == ICACHE_POLICY_AIVIVT)
> set_bit(ICACHEF_AIVIVT, &__icache_flags);
>
> pr_info("Detected %s I-cache on CPU%d", icache_policy_str[l1ip], cpu);
> --
> 1.8.3.2
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-08-04 10:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-08-04 8:16 [PATCH 1/3] arm64: fix typo in I-cache policy detection Ard Biesheuvel
2014-08-04 8:16 ` [PATCH 2/3] arm64: add helper functions to read I-cache attributes Ard Biesheuvel
2014-08-04 9:58 ` Mark Rutland
2014-08-04 10:38 ` Ard Biesheuvel
2014-08-04 8:16 ` [PATCH 3/3] arm64: don't flag non-aliasing VIPT I-caches as aliasing Ard Biesheuvel
2014-08-04 9:06 ` [PATCH 1/3] arm64: fix typo in I-cache policy detection Mark Rutland
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).