From: f.fainelli@gmail.com (Florian Fainelli)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] ARM: l2c: order optional properties in alphabetical order
Date: Wed, 13 Aug 2014 16:29:30 -0700 [thread overview]
Message-ID: <1407972571-8986-3-git-send-email-f.fainelli@gmail.com> (raw)
In-Reply-To: <1407972571-8986-1-git-send-email-f.fainelli@gmail.com>
Re-order the Level 2 cache controller binding optional properties into
alphabetical order.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
Documentation/devicetree/bindings/arm/l2cc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index af527ee111c2..b265ef25e55d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -43,9 +43,9 @@ Optional properties:
- arm,io-coherent : indicates that the system is operating in an hardware
I/O coherent mode. Valid only when the arm,pl310-cache compatible
string is used.
-- interrupts : 1 combined interrupt.
- cache-id-part: cache id part number to be used if it is not present
on hardware
+- interrupts : 1 combined interrupt.
- wt-override: If present then L2 is forced to Write through mode
Example:
--
1.9.1
next prev parent reply other threads:[~2014-08-13 23:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-13 23:29 [PATCH 0/3] ARM: l2c: cache size parsing through device tree Florian Fainelli
2014-08-13 23:29 ` [PATCH 1/3] ARM: l2c: enforce use of cache-level property Florian Fainelli
2014-08-13 23:29 ` Florian Fainelli [this message]
2014-08-13 23:29 ` [PATCH 3/3] ARM: l2c: parse 'cache-size' and 'cache-sets' properties Florian Fainelli
2014-08-23 1:59 ` [PATCH 0/3] ARM: l2c: cache size parsing through device tree Florian Fainelli
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