[PATCH 0/3] ARM: l2c: cache size parsing through device tree

[PATCH 0/3] ARM: l2c: cache size parsing through device tree

[Florian Fainelli]

Hi all,

This patch series adds support for specifying the L2 cache size through Device
Tree using the ePAPR standard 'cache-size' and 'cache-sets' properties.

The rationale behind these patches is to support Broadcom's BCM63138 DSL SoC
which comes out of reset with an invalid cache way-size specified in its L2C
auxiliary register.

For the third patch I took the approach of a helper function that can be called
by the 3 different of_parse functions that we have currently.

Thanks!

Florian Fainelli (3):
  ARM: l2c: enforce use of cache-level property
  ARM: l2c: order optional properties in alphabetical order
  ARM: l2c: parse 'cache-size' and 'cache-sets' properties

 Documentation/devicetree/bindings/arm/l2cc.txt |  4 +-
 arch/arm/mm/cache-l2x0.c                       | 68 ++++++++++++++++++++++++++
 2 files changed, 71 insertions(+), 1 deletion(-)

-- 
1.9.1

[PATCH 1/3] ARM: l2c: enforce use of cache-level property

[Florian Fainelli]

Make sure that we can read the "cache-level" property from the L2 cache
controller node, and ensure its value is 2.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/mm/cache-l2x0.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988a06ac..80488e78ce32 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1498,6 +1498,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	struct device_node *np;
 	struct resource res;
 	u32 cache_id, old_aux;
+	u32 cache_level = 2;
 
 	np = of_find_matching_node(NULL, l2x0_ids);
 	if (!np)
@@ -1530,6 +1531,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!of_property_read_bool(np, "cache-unified"))
 		pr_err("L2C: device tree omits to specify unified cache\n");
 
+	if (of_property_read_u32(np, "cache-level", &cache_level))
+		pr_err("L2C: device tree omits to specify cache-level\n");
+
+	if (cache_level != 2)
+		pr_err("L2C: device tree specifies invalid cache level\n");
+
 	/* L2 configuration can only be changed if the cache is disabled */
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
 		if (data->of_parse)
-- 
1.9.1

[PATCH 2/3] ARM: l2c: order optional properties in alphabetical order

[Florian Fainelli]

Re-order the Level 2 cache controller binding optional properties into
alphabetical order.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 Documentation/devicetree/bindings/arm/l2cc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index af527ee111c2..b265ef25e55d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -43,9 +43,9 @@ Optional properties:
 - arm,io-coherent : indicates that the system is operating in an hardware
   I/O coherent mode. Valid only when the arm,pl310-cache compatible
   string is used.
-- interrupts : 1 combined interrupt.
 - cache-id-part: cache id part number to be used if it is not present
   on hardware
+- interrupts : 1 combined interrupt.
 - wt-override: If present then L2 is forced to Write through mode
 
 Example:
-- 
1.9.1

[PATCH 3/3] ARM: l2c: parse 'cache-size' and 'cache-sets' properties

[Florian Fainelli]

When both 'cache-size' and 'cache-sets' are specified for a L2 cache
controller node, parse those properties and make sure we validate the
way_size based on which type of L2 cache controller we are using.

Update the L2 cache controller Device Tree binding with the optional
'cache-size' and 'cache-sets' properties.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 Documentation/devicetree/bindings/arm/l2cc.txt |  2 +
 arch/arm/mm/cache-l2x0.c                       | 61 ++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index b265ef25e55d..e5d9bbe540e2 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -45,6 +45,8 @@ Optional properties:
   string is used.
 - cache-id-part: cache id part number to be used if it is not present
   on hardware
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
 - interrupts : 1 combined interrupt.
 - wt-override: If present then L2 is forced to Write through mode
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 80488e78ce32..e681f36e9c07 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -945,6 +945,61 @@ static int l2_wt_override;
  * pass it though the device tree */
 static u32 cache_id_part_number_from_dt;
 
+static void __init l2x0_cache_size_of_parse(const struct device_node *np,
+					    u32 *aux_val, u32 *aux_mask,
+					    u32 max_way_size)
+{
+	u32 mask = 0, val = 0;
+	u32 size = 0, sets = 0;
+	u32 way_size = 0, way_size_bits = 1;
+
+	of_property_read_u32(np, "cache-size", &size);
+	of_property_read_u32(np, "cache-sets", &sets);
+
+	if (!size || !sets)
+		return;
+
+	way_size = size / sets;
+
+	if (way_size > max_way_size) {
+		pr_warn("L2C: way size %dKB is too large\n", way_size >> 10);
+		return;
+	}
+
+	way_size >>= 10;
+	switch (way_size) {
+	case 512:
+		way_size_bits = 6;
+		break;
+	case 256:
+		way_size_bits = 5;
+		break;
+	case 128:
+		way_size_bits = 4;
+		break;
+	case 64:
+		way_size_bits = 3;
+		break;
+	case 32:
+		way_size_bits = 2;
+		break;
+	case 16:
+		way_size_bits = 1;
+		break;
+	default:
+		pr_err("cache way size: %d KB is not mapped\n",
+		       way_size);
+		break;
+	}
+
+	mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
+	val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static void __init l2x0_of_parse(const struct device_node *np,
 				 u32 *aux_val, u32 *aux_mask)
 {
@@ -974,6 +1029,8 @@ static void __init l2x0_of_parse(const struct device_node *np,
 		val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
 	}
 
+	l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K);
+
 	*aux_val &= ~mask;
 	*aux_val |= val;
 	*aux_mask &= ~mask;
@@ -1047,6 +1104,8 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
 			       l2x0_base + L310_ADDR_FILTER_START);
 	}
+
+	l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_512K);
 }
 
 static const struct l2c_init_data of_l2c310_data __initconst = {
@@ -1253,6 +1312,8 @@ static void __init aurora_of_parse(const struct device_node *np,
 	*aux_val &= ~mask;
 	*aux_val |= val;
 	*aux_mask &= ~mask;
+
+	l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K);
 }
 
 static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
-- 
1.9.1

[PATCH 0/3] ARM: l2c: cache size parsing through device tree

[Florian Fainelli]

2014-08-13 16:29 GMT-07:00 Florian Fainelli <f.fainelli@gmail.com>:
> Hi all,
>
> This patch series adds support for specifying the L2 cache size through Device
> Tree using the ePAPR standard 'cache-size' and 'cache-sets' properties.
>
> The rationale behind these patches is to support Broadcom's BCM63138 DSL SoC
> which comes out of reset with an invalid cache way-size specified in its L2C
> auxiliary register.
>
> For the third patch I took the approach of a helper function that can be called
> by the 3 different of_parse functions that we have currently.

Russell, does that look like what you had in mind? Thank you!

>
> Thanks!
>
> Florian Fainelli (3):
>   ARM: l2c: enforce use of cache-level property
>   ARM: l2c: order optional properties in alphabetical order
>   ARM: l2c: parse 'cache-size' and 'cache-sets' properties
>
>  Documentation/devicetree/bindings/arm/l2cc.txt |  4 +-
>  arch/arm/mm/cache-l2x0.c                       | 68 ++++++++++++++++++++++++++
>  2 files changed, 71 insertions(+), 1 deletion(-)
>
> --
> 1.9.1
>



-- 
Florian