[PATCHv2 0/3] ARM: dts: socfpga: updates for SOCFPGA

[PATCHv2 0/3] ARM: dts: socfpga: updates for SOCFPGA

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Just a few DTS updates for the SOCFPGA platform.

v2:
patch 1/3 : same as v1
patch 2/3 : same as v1
patch 3/3 : Added a single line comment for /memreserve/

Dinh Nguyen (3):
  ARM: dts: socfpga: remove extra alias in the ArriaV devkit
  ARM: dts: socfpga: Add SD card detect
  ARM: dts: socfpga: memreserve first 4KB for SMP code

 arch/arm/boot/dts/socfpga_arria5.dtsi        | 2 ++
 arch/arm/boot/dts/socfpga_arria5_socdk.dts   | 7 -------
 arch/arm/boot/dts/socfpga_cyclone5.dtsi      | 4 +++-
 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 4 ++++
 4 files changed, 9 insertions(+), 8 deletions(-)

-- 
2.0.3

[PATCHv2 1/3] ARM: dts: socfpga: remove extra alias in the ArriaV devkit

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

commit [2755e187 dts: socfpga: Add DTS entry for adding the stmmac glue
layer for stmmac.] added an extra ethernet alias in the ArriaV devkit
board file. This patch removes it.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria5_socdk.dts | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index d532d17..27d551c 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,13 +37,6 @@
 		*/
 		ethernet0 = &gmac1;
 	};
-
-	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
-		 * to be added to the gmac1 device tree blob.
-		 */
-		ethernet0 = &gmac1;
-	};
 };
 
 &gmac1 {
-- 
2.0.3

[PATCHv2 2/3] ARM: dts: socfpga: Add SD card detect

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Revision D of the SOCFGPA devkit has a GPIO line used for SD/MMC card detect.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
---
 arch/arm/boot/dts/socfpga_cyclone5.dtsi      | 2 +-
 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 1ee03c4..33cad8b 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -28,7 +28,7 @@
 			};
 		};
 
-		dwmmc0 at ff704000 {
+		mmc0: dwmmc0 at ff704000 {
 			num-slots = <1>;
 			broken-cd;
 			bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 45de151..d7296a5 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -68,6 +68,10 @@
 	};
 };
 
+&mmc0 {
+	cd-gpios = <&gpio1 18 0>;
+};
+
 &usb1 {
 	status = "okay";
 };
-- 
2.0.3

[PATCHv2 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
bring secondary cores online. This patch adds a /memreserve/ section to
reserve the first 4K for the SMP trampoline code.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
---
v2: Add a comment in the dts files
---
 arch/arm/boot/dts/socfpga_arria5.dtsi   | 2 ++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 468fc4c..03e8268 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -15,6 +15,8 @@
  */
 
 /dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
 #include "socfpga.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 33cad8b..28c05e7 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -16,6 +16,8 @@
  */
 
 /dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
 #include "socfpga.dtsi"
 
 / {
-- 
2.0.3

[PATCHv2 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

[Mark Rutland]

Hi Dinh,

On Thu, Aug 14, 2014 at 10:13:34PM +0100, dinguyen at opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
> bring secondary cores online. This patch adds a /memreserve/ section to
> reserve the first 4K for the SMP trampoline code.

I'm slightly confused. 

Sorry to split hairs here, but I think the comment is subtly wrong.

The trampoline code seems to be placed in this location by Linux, so
it's not that we're protecting the trampoline code, but rather we're
preserving the location for future use.

I take it that the reset address isn't configurable?

Thanks,
Mark.

> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> Acked-by: Pavel Machek <pavel@denx.de>
> ---
> v2: Add a comment in the dts files
> ---
>  arch/arm/boot/dts/socfpga_arria5.dtsi   | 2 ++
>  arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
> index 468fc4c..03e8268 100644
> --- a/arch/arm/boot/dts/socfpga_arria5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
> @@ -15,6 +15,8 @@
>   */
>  
>  /dts-v1/;
> +/* First 4KB has trampoline code for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;
>  #include "socfpga.dtsi"
>  
>  / {
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> index 33cad8b..28c05e7 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> @@ -16,6 +16,8 @@
>   */
>  
>  /dts-v1/;
> +/* First 4KB has trampoline code for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;
>  #include "socfpga.dtsi"
>  
>  / {
> -- 
> 2.0.3
> 
> 

[PATCHv2 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

[Dinh Nguyen]

Hi Mark,

On 8/15/14, 6:27 AM, Mark Rutland wrote:
> Hi Dinh,
> 
> On Thu, Aug 14, 2014 at 10:13:34PM +0100, dinguyen at opensource.altera.com wrote:
>> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>>
>> The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
>> bring secondary cores online. This patch adds a /memreserve/ section to
>> reserve the first 4K for the SMP trampoline code.
> 
> I'm slightly confused. 
> 
> Sorry to split hairs here, but I think the comment is subtly wrong.
> 
> The trampoline code seems to be placed in this location by Linux, so
> it's not that we're protecting the trampoline code, but rather we're
> preserving the location for future use.

Yes, you're correct. Preserving this location for possible copying of
the trampoline code for SMP usage is more of a correct statement.
> 
> I take it that the reset address isn't configurable?

No, I don't believe it is on this platform.

Thanks for the review. I will spin a V3 with an updated commit message.

Dinh