* [PATCH] ARM: dts: Add sdio0 and sdio1 to the rk3288
@ 2014-08-14 5:49 Addy Ke
2014-08-14 15:47 ` Doug Anderson
2014-08-19 2:31 ` [PATCH v2] " Addy Ke
0 siblings, 2 replies; 8+ messages in thread
From: Addy Ke @ 2014-08-14 5:49 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
arch/arm/boot/dts/rk3288.dtsi | 76 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 7a9173d..a440869 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -120,6 +120,32 @@
//fifo-depth = <0x100>;
};
+ sdio0: dwmmc at ff0d0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ reg = <0xff0d0000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
+ clock-names = "biu", "ciu";
+
+ fifo-depth = <0x100>;
+ };
+
+ sdio1: dwmmc at ff0e0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ reg = <0xff0e0000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
+ clock-names = "biu", "ciu";
+
+ fifo-depth = <0x100>;
+ };
+
emmc: dwmmc at ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0xff0f0000 0x4000>;
@@ -589,6 +615,56 @@
};
};
+ sdio0 {
+ sdio0_clk: sdio0-clk {
+ rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwr: sdio0-pwr {
+ rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus1: sdio0-bus1 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
+ <4 21 RK_FUNC_1 &pcfg_pull_up>,
+ <4 22 RK_FUNC_1 &pcfg_pull_up>,
+ <4 23 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdio1 {
+ sdio1_clk: sdio1-clk {
+ rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_pwr: sdio1-pwr {
+ rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bus1: sdio1-bus1 {
+ rockchip,pins = <4 24 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
+ <3 25 RK_FUNC_4 &pcfg_pull_up>,
+ <3 26 RK_FUNC_4 &pcfg_pull_up>,
+ <3 27 RK_FUNC_4 &pcfg_pull_up>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-14 5:49 [PATCH] ARM: dts: Add sdio0 and sdio1 to the rk3288 Addy Ke
@ 2014-08-14 15:47 ` Doug Anderson
2014-08-19 2:31 ` [PATCH v2] " Addy Ke
1 sibling, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2014-08-14 15:47 UTC (permalink / raw)
To: linux-arm-kernel
Addy,
On Wed, Aug 13, 2014 at 10:49 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> arch/arm/boot/dts/rk3288.dtsi | 76 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 7a9173d..a440869 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -120,6 +120,32 @@
> //fifo-depth = <0x100>;
> };
>
> + sdio0: dwmmc at ff0d0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + reg = <0xff0d0000 0x4000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
> + clock-names = "biu", "ciu";
> +
> + fifo-depth = <0x100>;
> + };
Please repost and match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers. Specifically:
* No more #address-cells and #size-cells.
* By default status = "disabled".
* Sort properties alphabetically.
> +
> + sdio1: dwmmc at ff0e0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + reg = <0xff0e0000 0x4000>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
> + clock-names = "biu", "ciu";
> +
> + fifo-depth = <0x100>;
> + };
> +
> emmc: dwmmc at ff0f0000 {
> compatible = "rockchip,rk3288-dw-mshc";
> reg = <0xff0f0000 0x4000>;
> @@ -589,6 +615,56 @@
> };
> };
>
> + sdio0 {
> + sdio0_clk: sdio0-clk {
> + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + sdio0_cmd: sdio0-cmd {
> + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_pwr: sdio0-pwr {
> + rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bus1: sdio0-bus1 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bus4: sdio0-bus4 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
> + <4 21 RK_FUNC_1 &pcfg_pull_up>,
> + <4 22 RK_FUNC_1 &pcfg_pull_up>,
> + <4 23 RK_FUNC_1 &pcfg_pull_up>;
> + };
Can you add the card detect line here? How about the write protect
line? What about the "bkpwr" and "int" lines?
> + };
> +
> + sdio1 {
> + sdio1_clk: sdio1-clk {
> + rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
This requires that <https://patchwork.kernel.org/patch/4701721/> land
in order to compile. Since that hasn't landed you should explicitly
reference it.
> + };
> +
> + sdio1_cmd: sdio1-cmd {
> + rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_pwr: sdio1-pwr {
> + rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_bus1: sdio1-bus1 {
> + rockchip,pins = <4 24 RK_FUNC_4 &pcfg_pull_up>;
This is probably wrong and should be <3 24 ...>, not <4 24 ...>.
> + };
> +
> + sdio1_bus4: sdio1-bus4 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
> + <3 25 RK_FUNC_4 &pcfg_pull_up>,
> + <3 26 RK_FUNC_4 &pcfg_pull_up>,
> + <3 27 RK_FUNC_4 &pcfg_pull_up>;
> + };
> + };
> +
> emmc {
> emmc_clk: emmc-clk {
> rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-14 5:49 [PATCH] ARM: dts: Add sdio0 and sdio1 to the rk3288 Addy Ke
2014-08-14 15:47 ` Doug Anderson
@ 2014-08-19 2:31 ` Addy Ke
2014-08-19 8:15 ` [PATCH v3] " Addy Ke
2014-08-19 16:47 ` [PATCH v2] " Doug Anderson
1 sibling, 2 replies; 8+ messages in thread
From: Addy Ke @ 2014-08-19 2:31 UTC (permalink / raw)
To: linux-arm-kernel
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and "int" line, suggested by Doug Anderson
- fix up sdio1 configuration error
arch/arm/boot/dts/rk3288.dtsi | 86 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb..91576ae 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -88,6 +88,26 @@
status = "disabled";
};
+ sdio0: dwmmc at ff0d0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0d0000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio1: dwmmc at ff0e0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0e0000 0x4000>;
+ status = "disabled";
+ };
+
emmc: dwmmc at ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
@@ -508,6 +528,72 @@
};
};
+ sdio0 {
+ sdio0_clk: sdio0-clk {
+ rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_cd: sdio0-cd {
+ rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwr: sdio0-pwr {
+ rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_int: sdio0-int {
+ rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus1: sdio0-bus1 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
+ <4 21 RK_FUNC_1 &pcfg_pull_up>,
+ <4 22 RK_FUNC_1 &pcfg_pull_up>,
+ <4 23 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdio1 {
+ sdio1_clk: sdio1-clk {
+ rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_cd: sdio1-cd {
+ rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_pwr: sdio1-pwr {
+ rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_int: sdio1-int {
+ rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bus1: sdio1-bus1 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
+ <3 25 RK_FUNC_4 &pcfg_pull_up>,
+ <3 26 RK_FUNC_4 &pcfg_pull_up>,
+ <3 27 RK_FUNC_4 &pcfg_pull_up>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-19 2:31 ` [PATCH v2] " Addy Ke
@ 2014-08-19 8:15 ` Addy Ke
2014-08-19 10:21 ` [PATCH v4] " Addy Ke
2014-08-19 20:14 ` [PATCH v3] " Doug Anderson
2014-08-19 16:47 ` [PATCH v2] " Doug Anderson
1 sibling, 2 replies; 8+ messages in thread
From: Addy Ke @ 2014-08-19 8:15 UTC (permalink / raw)
To: linux-arm-kernel
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and "int" line, suggested by Doug Anderson
- fix up sdio1 configuration error
Changes in v3:
- sort sdio0 and sdio1 by pin number, suggested by Doug Anderson
- add "ro" and "bkpwr" line, suggested by Doug Anderson
arch/arm/boot/dts/rk3288.dtsi | 102 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb..12c0297 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -88,6 +88,26 @@
status = "disabled";
};
+ sdio0: dwmmc at ff0d0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0d0000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio1: dwmmc at ff0e0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0e0000 0x4000>;
+ status = "disabled";
+ };
+
emmc: dwmmc at ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
@@ -508,6 +528,88 @@
};
};
+ sdio0 {
+ sdio0_bus1: sdio0-bus1 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
+ <4 21 RK_FUNC_1 &pcfg_pull_up>,
+ <4 22 RK_FUNC_1 &pcfg_pull_up>,
+ <4 23 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio0_cd: sdio0-cd {
+ rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_ro: sdio0-ro {
+ rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwr: sdio0-pwr {
+ rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bkpwr: sdio0-bkpwr {
+ rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_int: sdio0-int {
+ rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdio1 {
+ sdio1_bus1: sdio1-bus1 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
+ <3 25 RK_FUNC_4 &pcfg_pull_up>,
+ <3 26 RK_FUNC_4 &pcfg_pull_up>,
+ <3 27 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_cd: sdio1-cd {
+ rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_ro: sdio1-ro {
+ rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bkpwr: sdio1-bkpwr {
+ rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_int: sdio1-int {
+ rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_clk: sdio1-clk {
+ rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ sdio1_pwr: sdio1-pwr {
+ rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-19 8:15 ` [PATCH v3] " Addy Ke
@ 2014-08-19 10:21 ` Addy Ke
2014-09-03 22:56 ` Heiko Stübner
2014-08-19 20:14 ` [PATCH v3] " Doug Anderson
1 sibling, 1 reply; 8+ messages in thread
From: Addy Ke @ 2014-08-19 10:21 UTC (permalink / raw)
To: linux-arm-kernel
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and "int" line, suggested by Doug Anderson
- fix up sdio1 configuration error
Changes in v3:
- sort sdio0 and sdio1 by pin number, suggested by Doug Anderson
- add "ro" and "bkpwr" line, suggested by Doug Anderson
Changes in v4:
- change "sdiox_ro" to "sdiox_wp", suggested by Doug Anderson
arch/arm/boot/dts/rk3288.dtsi | 102 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb..1fcc20e 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -88,6 +88,26 @@
status = "disabled";
};
+ sdio0: dwmmc at ff0d0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0d0000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio1: dwmmc at ff0e0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0e0000 0x4000>;
+ status = "disabled";
+ };
+
emmc: dwmmc at ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
@@ -508,6 +528,88 @@
};
};
+ sdio0 {
+ sdio0_bus1: sdio0-bus1 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
+ <4 21 RK_FUNC_1 &pcfg_pull_up>,
+ <4 22 RK_FUNC_1 &pcfg_pull_up>,
+ <4 23 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio0_cd: sdio0-cd {
+ rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_wp: sdio0-wp {
+ rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwr: sdio0-pwr {
+ rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bkpwr: sdio0-bkpwr {
+ rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_int: sdio0-int {
+ rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdio1 {
+ sdio1_bus1: sdio1-bus1 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
+ <3 25 RK_FUNC_4 &pcfg_pull_up>,
+ <3 26 RK_FUNC_4 &pcfg_pull_up>,
+ <3 27 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_cd: sdio1-cd {
+ rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_wp: sdio1-wp {
+ rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_bkpwr: sdio1-bkpwr {
+ rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_int: sdio1-int {
+ rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ sdio1_clk: sdio1-clk {
+ rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ sdio1_pwr: sdio1-pwr {
+ rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-19 2:31 ` [PATCH v2] " Addy Ke
2014-08-19 8:15 ` [PATCH v3] " Addy Ke
@ 2014-08-19 16:47 ` Doug Anderson
1 sibling, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2014-08-19 16:47 UTC (permalink / raw)
To: linux-arm-kernel
Addy,
On Mon, Aug 18, 2014 at 7:31 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
> This patch requires that <https://patchwork.kernel.org/patch/4701721/>
> land in order to compile.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> Changes in v2:
> - repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
> for the other dwmmc controllers
> - add "cd" and "int" line, suggested by Doug Anderson
> - fix up sdio1 configuration error
>
> arch/arm/boot/dts/rk3288.dtsi | 86 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 36be7bb..91576ae 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -88,6 +88,26 @@
> status = "disabled";
> };
>
> + sdio0: dwmmc at ff0d0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xff0d0000 0x4000>;
> + status = "disabled";
> + };
> +
> + sdio1: dwmmc at ff0e0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xff0e0000 0x4000>;
> + status = "disabled";
> + };
> +
> emmc: dwmmc at ff0f0000 {
> compatible = "rockchip,rk3288-dw-mshc";
> clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
> @@ -508,6 +528,72 @@
> };
> };
>
> + sdio0 {
> + sdio0_clk: sdio0-clk {
> + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + sdio0_cmd: sdio0-cmd {
> + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_cd: sdio0-cd {
> + rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_pwr: sdio0-pwr {
> + rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_int: sdio0-int {
> + rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bus1: sdio0-bus1 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bus4: sdio0-bus4 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
> + <4 21 RK_FUNC_1 &pcfg_pull_up>,
> + <4 22 RK_FUNC_1 &pcfg_pull_up>,
> + <4 23 RK_FUNC_1 &pcfg_pull_up>;
> + };
Can you make sure to include all of the sdio0 pins? I think you're
still missing gpio4d3 (write protect). You're also missing gpio4d5
(bkpwr), not that I know what that actually is.
Also: I know that sdmmc isn't sorted properly (should probably fix
that), but can you sort sdio0 and sdio1 by pin number? So list data
lines first, then cmd, then clock, then detect, then write protect,
...
Same comments apply to sdio1.
> + };
> +
> + sdio1 {
> + sdio1_clk: sdio1-clk {
> + rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
> + };
> +
> + sdio1_cmd: sdio1-cmd {
> + rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_cd: sdio1-cd {
> + rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_pwr: sdio1-pwr {
> + rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_int: sdio1-int {
> + rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_bus1: sdio1-bus1 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_bus4: sdio1-bus4 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
> + <3 25 RK_FUNC_4 &pcfg_pull_up>,
> + <3 26 RK_FUNC_4 &pcfg_pull_up>,
> + <3 27 RK_FUNC_4 &pcfg_pull_up>;
> + };
> + };
> +
> emmc {
> emmc_clk: emmc-clk {
> rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
> --
> 1.8.3.2
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-19 8:15 ` [PATCH v3] " Addy Ke
2014-08-19 10:21 ` [PATCH v4] " Addy Ke
@ 2014-08-19 20:14 ` Doug Anderson
1 sibling, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2014-08-19 20:14 UTC (permalink / raw)
To: linux-arm-kernel
Addy,
On Tue, Aug 19, 2014 at 1:15 AM, Addy Ke <addy.ke@rock-chips.com> wrote:
> This patch requires that <https://patchwork.kernel.org/patch/4701721/>
> land in order to compile.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> Changes in v2:
> - repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
> for the other dwmmc controllers
> - add "cd" and "int" line, suggested by Doug Anderson
> - fix up sdio1 configuration error
>
> Changes in v3:
> - sort sdio0 and sdio1 by pin number, suggested by Doug Anderson
> - add "ro" and "bkpwr" line, suggested by Doug Anderson
>
> arch/arm/boot/dts/rk3288.dtsi | 102 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 36be7bb..12c0297 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -88,6 +88,26 @@
> status = "disabled";
> };
>
> + sdio0: dwmmc at ff0d0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xff0d0000 0x4000>;
> + status = "disabled";
> + };
> +
> + sdio1: dwmmc at ff0e0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xff0e0000 0x4000>;
> + status = "disabled";
> + };
> +
> emmc: dwmmc at ff0f0000 {
> compatible = "rockchip,rk3288-dw-mshc";
> clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
> @@ -508,6 +528,88 @@
> };
> };
>
> + sdio0 {
> + sdio0_bus1: sdio0-bus1 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bus4: sdio0-bus4 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
> + <4 21 RK_FUNC_1 &pcfg_pull_up>,
> + <4 22 RK_FUNC_1 &pcfg_pull_up>,
> + <4 23 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_cmd: sdio0-cmd {
> + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_clk: sdio0-clk {
> + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + sdio0_cd: sdio0-cd {
> + rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_ro: sdio0-ro {
I probably would have called it "sdio0-wp", not "sdio-ro". That
matches the syntax used elsewhere ("wp-gpios", "disable-wp", etc).
Can you do one more spin?
With that change, you can add my Reviewed-by tag.
> + rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_pwr: sdio0-pwr {
> + rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bkpwr: sdio0-bkpwr {
> + rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_int: sdio0-int {
> + rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
> + };
> + };
> +
> + sdio1 {
> + sdio1_bus1: sdio1-bus1 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_bus4: sdio1-bus4 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
> + <3 25 RK_FUNC_4 &pcfg_pull_up>,
> + <3 26 RK_FUNC_4 &pcfg_pull_up>,
> + <3 27 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_cd: sdio1-cd {
> + rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_ro: sdio1-ro {
Here, too.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4] ARM: dts: Add sdio0 and sdio1 to the rk3288
2014-08-19 10:21 ` [PATCH v4] " Addy Ke
@ 2014-09-03 22:56 ` Heiko Stübner
0 siblings, 0 replies; 8+ messages in thread
From: Heiko Stübner @ 2014-09-03 22:56 UTC (permalink / raw)
To: linux-arm-kernel
Am Dienstag, 19. August 2014, 18:21:08 schrieb Addy Ke:
> This patch requires that <https://patchwork.kernel.org/patch/4701721/>
> land in order to compile.
>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
I've added the patch to my v3.18-next/dts branch
> ---
> Changes in v2:
> - repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
> for the other dwmmc controllers
> - add "cd" and "int" line, suggested by Doug Anderson
> - fix up sdio1 configuration error
>
> Changes in v3:
> - sort sdio0 and sdio1 by pin number, suggested by Doug Anderson
> - add "ro" and "bkpwr" line, suggested by Doug Anderson
>
> Changes in v4:
> - change "sdiox_ro" to "sdiox_wp", suggested by Doug Anderson
>
> arch/arm/boot/dts/rk3288.dtsi | 102
> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102
> insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 36be7bb..1fcc20e 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -88,6 +88,26 @@
> status = "disabled";
> };
>
> + sdio0: dwmmc at ff0d0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xff0d0000 0x4000>;
> + status = "disabled";
> + };
> +
> + sdio1: dwmmc at ff0e0000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xff0e0000 0x4000>;
> + status = "disabled";
> + };
> +
> emmc: dwmmc at ff0f0000 {
> compatible = "rockchip,rk3288-dw-mshc";
> clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
> @@ -508,6 +528,88 @@
> };
> };
>
> + sdio0 {
> + sdio0_bus1: sdio0-bus1 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bus4: sdio0-bus4 {
> + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
> + <4 21 RK_FUNC_1 &pcfg_pull_up>,
> + <4 22 RK_FUNC_1 &pcfg_pull_up>,
> + <4 23 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_cmd: sdio0-cmd {
> + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_clk: sdio0-clk {
> + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + sdio0_cd: sdio0-cd {
> + rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_wp: sdio0-wp {
> + rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_pwr: sdio0-pwr {
> + rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_bkpwr: sdio0-bkpwr {
> + rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
> + };
> +
> + sdio0_int: sdio0-int {
> + rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
> + };
> + };
> +
> + sdio1 {
> + sdio1_bus1: sdio1-bus1 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_bus4: sdio1-bus4 {
> + rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
> + <3 25 RK_FUNC_4 &pcfg_pull_up>,
> + <3 26 RK_FUNC_4 &pcfg_pull_up>,
> + <3 27 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_cd: sdio1-cd {
> + rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_wp: sdio1-wp {
> + rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_bkpwr: sdio1-bkpwr {
> + rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_int: sdio1-int {
> + rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_cmd: sdio1-cmd {
> + rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
> + };
> +
> + sdio1_clk: sdio1-clk {
> + rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
> + };
> +
> + sdio1_pwr: sdio1-pwr {
> + rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
> + };
> + };
> +
> emmc {
> emmc_clk: emmc-clk {
> rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2014-09-03 22:56 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-08-14 5:49 [PATCH] ARM: dts: Add sdio0 and sdio1 to the rk3288 Addy Ke
2014-08-14 15:47 ` Doug Anderson
2014-08-19 2:31 ` [PATCH v2] " Addy Ke
2014-08-19 8:15 ` [PATCH v3] " Addy Ke
2014-08-19 10:21 ` [PATCH v4] " Addy Ke
2014-09-03 22:56 ` Heiko Stübner
2014-08-19 20:14 ` [PATCH v3] " Doug Anderson
2014-08-19 16:47 ` [PATCH v2] " Doug Anderson
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