* [PATCH v4 1/4] pwm: rockchip: Allow polarity invert on rk3288
2014-08-20 18:53 [PATCH v4 0/4] PWM changes for rk3288-evb Doug Anderson
@ 2014-08-20 18:53 ` Doug Anderson
2014-08-20 18:54 ` [PATCH v4 2/4] ARM: rockchip: rk3288: Switch to use the proper PWM IP Doug Anderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Doug Anderson @ 2014-08-20 18:53 UTC (permalink / raw)
To: linux-arm-kernel
The rk3288 has the ability to invert the polarity of the PWM. Let's
enable that ability. Note that this increases pwm_cells to 3 for
rk3288.
Signed-off-by: Doug Anderson <dianders@chromium.org>
---
Changes in v4:
- Updated comment not to add caveats about pwm_cells 3.
- rockchip_pwm_set_polarity() is now static.
- Separate pwm_ops for v1 and v2; no set_polarity() in v1.
- Added a blank line.
Changes in v3:
- Don't store a private copy of polarity.
- Use true instead of 1.
- Cleanup init order with "has_invert".
Changes in v2: None
.../devicetree/bindings/pwm/pwm-rockchip.txt | 4 +-
drivers/pwm/pwm-rockchip.c | 57 ++++++++++++++++++----
2 files changed, 50 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
index d47d15a..b8be3d0 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
@@ -7,8 +7,8 @@ Required properties:
"rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
- reg: physical base address and length of the controller's registers
- clocks: phandle and clock specifier of the PWM reference clock
- - #pwm-cells: should be 2. See pwm.txt in this directory for a
- description of the cell format.
+ - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
+ for a description of the cell format.
Example:
diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index bdd8644..9442df2 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -24,7 +24,9 @@
#define PWM_ENABLE (1 << 0)
#define PWM_CONTINUOUS (1 << 1)
#define PWM_DUTY_POSITIVE (1 << 3)
+#define PWM_DUTY_NEGATIVE (0 << 3)
#define PWM_INACTIVE_NEGATIVE (0 << 4)
+#define PWM_INACTIVE_POSITIVE (1 << 4)
#define PWM_OUTPUT_LEFT (0 << 5)
#define PWM_LP_DISABLE (0 << 8)
@@ -45,8 +47,10 @@ struct rockchip_pwm_regs {
struct rockchip_pwm_data {
struct rockchip_pwm_regs regs;
unsigned int prescaler;
+ const struct pwm_ops *ops;
- void (*set_enable)(struct pwm_chip *chip, bool enable);
+ void (*set_enable)(struct pwm_chip *chip,
+ struct pwm_device *pwm, bool enable);
};
static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
@@ -54,7 +58,8 @@ static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
return container_of(c, struct rockchip_pwm_chip, chip);
}
-static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
+static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
+ struct pwm_device *pwm, bool enable)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
@@ -70,14 +75,19 @@ static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
writel_relaxed(val, pc->base + pc->data->regs.ctrl);
}
-static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
+static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
+ struct pwm_device *pwm, bool enable)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
- PWM_CONTINUOUS | PWM_DUTY_POSITIVE |
- PWM_INACTIVE_NEGATIVE;
+ PWM_CONTINUOUS;
u32 val;
+ if (pwm->polarity == PWM_POLARITY_INVERSED)
+ enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
+ else
+ enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
+
val = readl_relaxed(pc->base + pc->data->regs.ctrl);
if (enable)
@@ -124,6 +134,19 @@ static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
+static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ /*
+ * No action needed here because pwm->polarity will be set by the core
+ * and the core will only change polarity when the PWM is not enabled.
+ * We'll handle things in set_enable().
+ */
+
+ return 0;
+}
+
static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
@@ -133,7 +156,7 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
if (ret)
return ret;
- pc->data->set_enable(chip, true);
+ pc->data->set_enable(chip, pwm, true);
return 0;
}
@@ -142,18 +165,26 @@ static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
- pc->data->set_enable(chip, false);
+ pc->data->set_enable(chip, pwm, false);
clk_disable(pc->clk);
}
-static const struct pwm_ops rockchip_pwm_ops = {
+static const struct pwm_ops rockchip_pwm_ops_v1 = {
.config = rockchip_pwm_config,
.enable = rockchip_pwm_enable,
.disable = rockchip_pwm_disable,
.owner = THIS_MODULE,
};
+static const struct pwm_ops rockchip_pwm_ops_v2 = {
+ .config = rockchip_pwm_config,
+ .set_polarity = rockchip_pwm_set_polarity,
+ .enable = rockchip_pwm_enable,
+ .disable = rockchip_pwm_disable,
+ .owner = THIS_MODULE,
+};
+
static const struct rockchip_pwm_data pwm_data_v1 = {
.regs = {
.duty = 0x04,
@@ -162,6 +193,7 @@ static const struct rockchip_pwm_data pwm_data_v1 = {
.ctrl = 0x0c,
},
.prescaler = 2,
+ .ops = &rockchip_pwm_ops_v1,
.set_enable = rockchip_pwm_set_enable_v1,
};
@@ -173,6 +205,7 @@ static const struct rockchip_pwm_data pwm_data_v2 = {
.ctrl = 0x0c,
},
.prescaler = 1,
+ .ops = &rockchip_pwm_ops_v2,
.set_enable = rockchip_pwm_set_enable_v2,
};
@@ -184,6 +217,7 @@ static const struct rockchip_pwm_data pwm_data_vop = {
.ctrl = 0x00,
},
.prescaler = 1,
+ .ops = &rockchip_pwm_ops_v2,
.set_enable = rockchip_pwm_set_enable_v2,
};
@@ -227,10 +261,15 @@ static int rockchip_pwm_probe(struct platform_device *pdev)
pc->data = id->data;
pc->chip.dev = &pdev->dev;
- pc->chip.ops = &rockchip_pwm_ops;
+ pc->chip.ops = pc->data->ops;
pc->chip.base = -1;
pc->chip.npwm = 1;
+ if (pc->data->ops->set_polarity) {
+ pc->chip.of_xlate = of_pwm_xlate_with_flags;
+ pc->chip.of_pwm_n_cells = 3;
+ }
+
ret = pwmchip_add(&pc->chip);
if (ret < 0) {
clk_unprepare(pc->clk);
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v4 2/4] ARM: rockchip: rk3288: Switch to use the proper PWM IP
2014-08-20 18:53 [PATCH v4 0/4] PWM changes for rk3288-evb Doug Anderson
2014-08-20 18:53 ` [PATCH v4 1/4] pwm: rockchip: Allow polarity invert on rk3288 Doug Anderson
@ 2014-08-20 18:54 ` Doug Anderson
2014-08-20 18:54 ` [PATCH v4 3/4] ARM: dts: Add main PWM info to rk3288 Doug Anderson
2014-08-20 18:54 ` [PATCH v4 4/4] ARM: dts: Enable PWM backlight on rk3288-evb Doug Anderson
3 siblings, 0 replies; 5+ messages in thread
From: Doug Anderson @ 2014-08-20 18:54 UTC (permalink / raw)
To: linux-arm-kernel
The rk3288 SoC has an option to switch all of the PWMs in the system
between the old IP block and the new IP block. The rk3288 PWM driver
is written for the new block, so make sure that we enable the new
block in the GRF (general register file) when the PWM driver probes.
We emulate the solution to this problem used in i2c-rk3x.c. One
difference for the PWM is that there's a single "enable new IP" that's
used for all 4 PWMs. That means we set this bit 4 times if we've got
all 4 PWMs enabled. That shouldn't hurt.
Signed-off-by: Doug Anderson <dianders@chromium.org>
---
Changes in v4:
- Totally rewrote to go in the PWM driver.
- Reordered IP switch to be atop invert patch.
Changes in v3: None
Changes in v2:
- Check for failed ioremap()
.../devicetree/bindings/pwm/pwm-rockchip.txt | 4 +++
drivers/pwm/pwm-rockchip.c | 29 ++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
index b8be3d0..39190ec 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
@@ -10,6 +10,10 @@ Required properties:
- #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
for a description of the cell format.
+Required for "rockchip,rk3288-pwm":
+ - rockchip,grf : the phandle of the syscon node for the general register
+ file (GRF)
+
Example:
pwm0: pwm at 20030000 {
diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index 9442df2..08cbde6 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -16,7 +16,12 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/regmap.h>
#include <linux/time.h>
+#include <linux/mfd/syscon.h>
+
+#define RK3288_GRF_PWM_ENABLE_OFFSET 0x024c
+#define RK3288_GRF_PWM_ENABLE_BIT 0
#define PWM_CTRL_TIMER_EN (1 << 0)
#define PWM_CTRL_OUTPUT_EN (1 << 3)
@@ -231,6 +236,7 @@ MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
static int rockchip_pwm_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
const struct of_device_id *id;
struct rockchip_pwm_chip *pc;
struct resource *r;
@@ -240,6 +246,29 @@ static int rockchip_pwm_probe(struct platform_device *pdev)
if (!id)
return -EINVAL;
+ /*
+ * Switch to new interface on rk3288.
+ * The control bit is located in the GRF register space.
+ */
+ if (of_device_is_compatible(np, "rockchip,rk3288-pwm")) {
+ struct regmap *grf;
+
+ grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(grf)) {
+ dev_err(&pdev->dev, "Missing rockchip,grf property\n");
+ return PTR_ERR(grf);
+ }
+
+ /* Set bit 16 for write mask, 0 for switch to new IP */
+ ret = regmap_write(grf, RK3288_GRF_PWM_ENABLE_OFFSET,
+ BIT(RK3288_GRF_PWM_ENABLE_BIT + 16) |
+ BIT(RK3288_GRF_PWM_ENABLE_BIT));
+ if (ret != 0) {
+ dev_err(&pdev->dev, "Could not access GRF: %d\n", ret);
+ return ret;
+ }
+ }
+
pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
if (!pc)
return -ENOMEM;
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v4 3/4] ARM: dts: Add main PWM info to rk3288
2014-08-20 18:53 [PATCH v4 0/4] PWM changes for rk3288-evb Doug Anderson
2014-08-20 18:53 ` [PATCH v4 1/4] pwm: rockchip: Allow polarity invert on rk3288 Doug Anderson
2014-08-20 18:54 ` [PATCH v4 2/4] ARM: rockchip: rk3288: Switch to use the proper PWM IP Doug Anderson
@ 2014-08-20 18:54 ` Doug Anderson
2014-08-20 18:54 ` [PATCH v4 4/4] ARM: dts: Enable PWM backlight on rk3288-evb Doug Anderson
3 siblings, 0 replies; 5+ messages in thread
From: Doug Anderson @ 2014-08-20 18:54 UTC (permalink / raw)
To: linux-arm-kernel
This adds the PWM info (other than the VOP PWM) to the main rk3288
dtsi file.
Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
---
Changes in v4:
- Add rockchip,grf to pwm nodes.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 36be7bb..9074205 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -261,6 +261,54 @@
status = "disabled";
};
+ pwm0: pwm at ff680000 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0xff680000 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ pwm1: pwm at ff680010 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0xff680010 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ pwm2: pwm at ff680020 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0xff680020 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ pwm3: pwm at ff680030 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0xff680030 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
pmu: power-management at ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
@@ -611,5 +659,29 @@
rockchip,pins = <5 15 3 &pcfg_pull_none>;
};
};
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
};
};
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply related [flat|nested] 5+ messages in thread