From mboxrd@z Thu Jan 1 00:00:00 1970 From: abrestic@chromium.org (Andrew Bresticker) Date: Tue, 2 Sep 2014 14:34:59 -0700 Subject: [PATCH v3 7/9] ARM: tegra: Add Tegra124 XUSB mailbox and xHCI controller In-Reply-To: <1409693701-16520-1-git-send-email-abrestic@chromium.org> References: <1409693701-16520-1-git-send-email-abrestic@chromium.org> Message-ID: <1409693701-16520-8-git-send-email-abrestic@chromium.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add nodes for the Tegra XUSB mailbox and Tegra xHCI controller and add the PHY mailbox channel to the XUSB padctl node. Signed-off-by: Andrew Bresticker --- Changes from v2: - Dropped channel specifier from mailbox bindings. - Added mbox-names properties. Changes from v1: - Updated to use common mailbox bindings. - Added remaining clocks/resets. --- arch/arm/boot/dts/tegra124.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 03916ef..89afd45 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -495,11 +495,52 @@ status = "disabled"; }; + usb at 0,70090000 { + compatible = "nvidia,tegra124-xhci"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_DEV>, + <&tegra_car TEGRA124_CLK_XUSB_DEV_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", "xusb_dev", + "xusb_dev_src", "xusb_falcon_src", "xusb_ss", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 95>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_dev", "xusb_ss", "xusb"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; + status = "disabled"; + }; + + xusb_mbox: mailbox at 0,70098000 { + compatible = "nvidia,tegra124-xusb-mbox"; + reg = <0x0 0x70098000 0x0 0x1000>; + interrupts = ; + + #mbox-cells = <0>; + }; + padctl: padctl at 0,7009f000 { compatible = "nvidia,tegra124-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; #phy-cells = <1>; }; -- 2.1.0.rc2.206.gedb03e5