* [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
2014-09-30 3:12 [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate Jianqun
@ 2014-09-30 3:38 ` Kever Yang
2014-09-30 3:44 ` Jianqun
2014-10-11 18:54 ` Heiko Stübner
2014-10-13 0:44 ` [PATCH v2] " Jianqun
2 siblings, 1 reply; 7+ messages in thread
From: Kever Yang @ 2014-09-30 3:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jianqun,
pls add linux-rockchip at lists.infradead.org next time.
On 09/30/2014 11:12 AM, Jianqun wrote:
> The relation of i2s nodes as follows:
> i2s_src 0 0 594000000 0
> i2s_frac 0 0 11289600 0
> i2s_pre 0 0 11289600 0
> sclk_i2s0 0 0 11289600 0
> i2s0_clkout 0 0 11289600 0
> hclk_i2s0 1 1 99000000 0
I always got the result as following when I set sclk_i2s0 to 11289600,
any one knows the reason?
gpll 6 6 594000000 0
sclk_emmc 1 1 99000000 0
i2s_src 0 0 11207548 0
i2s_pre 0 0 11207548 0
sclk_i2s0 0 0 11207548 0
i2s0_clkout 0 0 11207548 0
i2s_frac 0 0 646456897 0
> sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
> allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
> "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".
>
> Tested on rk3288 board using max98090, with command "aplay <music.wav>"
>
> Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
> Signed-off-by: Jianqun <jay.xu@rock-chips.com>
> ---
> drivers/clk/rockchip/clk-rk3288.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> index c770de0..baf19b4 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -301,15 +301,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
> RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
> RK3288_CLKGATE_CON(4), 1, GFLAGS),
> - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
> + COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(8), 0,
> RK3288_CLKGATE_CON(4), 2, GFLAGS),
> - MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
> + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
> - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
> + COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
> RK3288_CLKGATE_CON(4), 0, GFLAGS),
> - GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
> + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
> RK3288_CLKGATE_CON(4), 3, GFLAGS),
>
> MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
2014-09-30 3:38 ` Kever Yang
@ 2014-09-30 3:44 ` Jianqun
0 siblings, 0 replies; 7+ messages in thread
From: Jianqun @ 2014-09-30 3:44 UTC (permalink / raw)
To: linux-arm-kernel
? 09/30/2014 11:38 AM, Kever Yang ??:
> Hi Jianqun,
>
> pls add linux-rockchip at lists.infradead.org next time.
>
OK, thanks
> On 09/30/2014 11:12 AM, Jianqun wrote:
>> The relation of i2s nodes as follows:
>> i2s_src 0 0 594000000 0
>> i2s_frac 0 0 11289600 0
>> i2s_pre 0 0 11289600 0
>> sclk_i2s0 0 0 11289600 0
>> i2s0_clkout 0 0 11289600 0
>> hclk_i2s0 1 1 99000000 0
> I always got the result as following when I set sclk_i2s0 to 11289600,
> any one knows the reason?
>
> gpll 6 6 594000000 0
> sclk_emmc 1 1 99000000 0
> i2s_src 0 0 11207548 0
> i2s_pre 0 0 11207548 0
> sclk_i2s0 0 0 11207548 0
> i2s0_clkout 0 0 11207548 0
> i2s_frac 0 0 646456897 0
Hi, as clock tree shows, i2s_pre should come from i2s_frac, that's the root different above two trees.
>> sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
>> allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
>> "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".
>>
>> Tested on rk3288 board using max98090, with command "aplay <music.wav>"
>>
>> Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
>> Signed-off-by: Jianqun <jay.xu@rock-chips.com>
>> ---
>> drivers/clk/rockchip/clk-rk3288.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
>> index c770de0..baf19b4 100644
>> --- a/drivers/clk/rockchip/clk-rk3288.c
>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>> @@ -301,15 +301,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
>> COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
>> RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
>> RK3288_CLKGATE_CON(4), 1, GFLAGS),
>> - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
>> + COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
>> RK3288_CLKSEL_CON(8), 0,
>> RK3288_CLKGATE_CON(4), 2, GFLAGS),
>> - MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
>> + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
>> RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
>> - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
>> + COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
>> RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
>> RK3288_CLKGATE_CON(4), 0, GFLAGS),
>> - GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
>> + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
>> RK3288_CLKGATE_CON(4), 3, GFLAGS),
>> MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
>
>
>
>
--
Jianqun Xu
****************************************************************************
*IMPORTANT NOTICE:*This email is from Fuzhou Rockchip Electronics Co.,
Ltd .The contents of this email and any attachments may contain
information that is privileged, confidential and/or exempt from
disclosure under applicable law and relevant NDA. If you are not the
intended recipient, you are hereby notified that any disclosure,
copying, distribution, or use of the information is STRICTLY PROHIBITED.
Please immediately contact the sender as soon as possible and destroy
the material in its entirety in any format. Thank you.
****************************************************************************
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
2014-09-30 3:12 [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate Jianqun
2014-09-30 3:38 ` Kever Yang
@ 2014-10-11 18:54 ` Heiko Stübner
2014-10-13 0:32 ` Jianqun
2014-10-13 0:44 ` [PATCH v2] " Jianqun
2 siblings, 1 reply; 7+ messages in thread
From: Heiko Stübner @ 2014-10-11 18:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jianqun,
Am Dienstag, 30. September 2014, 11:12:04 schrieb Jianqun:
> The relation of i2s nodes as follows:
> i2s_src 0 0 594000000 0
> i2s_frac 0 0 11289600 0
> i2s_pre 0 0 11289600 0
> sclk_i2s0 0 0 11289600 0
> i2s0_clkout 0 0 11289600 0
> hclk_i2s0 1 1 99000000 0
>
> sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
> allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
> "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".
>
> Tested on rk3288 board using max98090, with command "aplay <music.wav>"
>
> Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
Please no "Change-Id"s in upstream patches.
> Signed-off-by: Jianqun <jay.xu@rock-chips.com>
> ---
> drivers/clk/rockchip/clk-rk3288.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index c770de0..baf19b4 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -301,15 +301,15 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = { COMPOSITE(0, "i2s_src",
> mux_pll_src_cpll_gpll_p, 0,
> RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
> RK3288_CLKGATE_CON(4), 1, GFLAGS),
> - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
> + COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(8), 0,
> RK3288_CLKGATE_CON(4), 2, GFLAGS),
> - MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
> + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
> - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
> + COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
are you sure it is correct that i2s0_clkout should also be able to set the
core i2s clock?
I.e. as it is now, the i2s controller could set one frequency through
sclk_i2s0 and whatever uses i2s0_clkout would be able to set it to something
completely different, which may call for trouble.
So in my mind, it might be better to limit i2s0_clkout to select between its
two parent without being able influence the core i2s clock?
Heiko
> RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
> RK3288_CLKGATE_CON(4), 0, GFLAGS),
> - GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
> + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
> RK3288_CLKGATE_CON(4), 3, GFLAGS),
>
> MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
2014-10-11 18:54 ` Heiko Stübner
@ 2014-10-13 0:32 ` Jianqun
0 siblings, 0 replies; 7+ messages in thread
From: Jianqun @ 2014-10-13 0:32 UTC (permalink / raw)
To: linux-arm-kernel
? 10/12/2014 02:54 AM, Heiko St?bner ??:
> Hi Jianqun,
>
> Am Dienstag, 30. September 2014, 11:12:04 schrieb Jianqun:
>> The relation of i2s nodes as follows:
>> i2s_src 0 0 594000000 0
>> i2s_frac 0 0 11289600 0
>> i2s_pre 0 0 11289600 0
>> sclk_i2s0 0 0 11289600 0
>> i2s0_clkout 0 0 11289600 0
>> hclk_i2s0 1 1 99000000 0
>>
>> sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
>> allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
>> "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".
>>
>> Tested on rk3288 board using max98090, with command "aplay <music.wav>"
>>
>> Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
> Please no "Change-Id"s in upstream patches.
ok
>
>
>> Signed-off-by: Jianqun <jay.xu@rock-chips.com>
>> ---
>> drivers/clk/rockchip/clk-rk3288.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3288.c
>> b/drivers/clk/rockchip/clk-rk3288.c index c770de0..baf19b4 100644
>> --- a/drivers/clk/rockchip/clk-rk3288.c
>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>> @@ -301,15 +301,15 @@ static struct rockchip_clk_branch
>> rk3288_clk_branches[] __initdata = { COMPOSITE(0, "i2s_src",
>> mux_pll_src_cpll_gpll_p, 0,
>> RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
>> RK3288_CLKGATE_CON(4), 1, GFLAGS),
>> - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
>> + COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
>> RK3288_CLKSEL_CON(8), 0,
>> RK3288_CLKGATE_CON(4), 2, GFLAGS),
>> - MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
>> + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
>> RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
>> - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
>> + COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
> are you sure it is correct that i2s0_clkout should also be able to set the
> core i2s clock?
>
> I.e. as it is now, the i2s controller could set one frequency through
> sclk_i2s0 and whatever uses i2s0_clkout would be able to set it to something
> completely different, which may call for trouble.
>
> So in my mind, it might be better to limit i2s0_clkout to select between its
> two parent without being able influence the core i2s clock?
ok, you are right, here is the new clock tree with your suggestion, when play music
i2s_src 1 1 594000000 0
i2s_frac 1 1 11289600 0
i2s_pre 1 1 11289600 0
sclk_i2s0 1 1 11289600 0
i2s0_clkout 0 0 11289600 0
hclk_i2s0 1 1 148500000 0
I'll make an patch v2 soon
>
> Heiko
>
>
>> RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
>> RK3288_CLKGATE_CON(4), 0, GFLAGS),
>> - GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
>> + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
>> RK3288_CLKGATE_CON(4), 3, GFLAGS),
>>
>> MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
>
>
>
--
Jianqun Xu
****************************************************************************
*IMPORTANT NOTICE:*This email is from Fuzhou Rockchip Electronics Co.,
Ltd .The contents of this email and any attachments may contain
information that is privileged, confidential and/or exempt from
disclosure under applicable law and relevant NDA. If you are not the
intended recipient, you are hereby notified that any disclosure,
copying, distribution, or use of the information is STRICTLY PROHIBITED.
Please immediately contact the sender as soon as possible and destroy
the material in its entirety in any format. Thank you.
****************************************************************************
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
2014-09-30 3:12 [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate Jianqun
2014-09-30 3:38 ` Kever Yang
2014-10-11 18:54 ` Heiko Stübner
@ 2014-10-13 0:44 ` Jianqun
2014-10-16 19:17 ` Heiko Stübner
2 siblings, 1 reply; 7+ messages in thread
From: Jianqun @ 2014-10-13 0:44 UTC (permalink / raw)
To: linux-arm-kernel
The relation of i2s nodes as follows:
i2s_src 1 1 594000000 0
i2s_frac 1 1 11289600 0
i2s_pre 1 1 11289600 0
sclk_i2s0 1 1 11289600 0
i2s0_clkout 0 0 11289600 0
hclk_i2s0 1 1 148500000 0
"sclk_i2s0" is the master clock, should allow to set its parent's rate.
Add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre" and "sclk_i2s0".
Tested on rk3288 board using max98090, with command "aplay <music.wav>"
and cat /sys/kernel/debug/clk/clk_summary |grep i2s
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
---
change since v1:
- no "Change-Id"s in upstream patches, suggested by Heiko
- to limit i2s0_clkout to select between its two parent without being able
influence the core i2s clock, suggested by Heiko
drivers/clk/rockchip/clk-rk3288.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index b22a2d2..ae32d78 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -238,15 +238,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 1, GFLAGS),
- COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
+ COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(8), 0,
RK3288_CLKGATE_CON(4), 2, GFLAGS),
- MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
+ MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
RK3288_CLKGATE_CON(4), 0, GFLAGS),
- GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
+ GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 3, GFLAGS),
MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
2014-10-13 0:44 ` [PATCH v2] " Jianqun
@ 2014-10-16 19:17 ` Heiko Stübner
0 siblings, 0 replies; 7+ messages in thread
From: Heiko Stübner @ 2014-10-16 19:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jianqun,
Am Montag, 13. Oktober 2014, 08:44:16 schrieb Jianqun:
> The relation of i2s nodes as follows:
> i2s_src 1 1 594000000 0
> i2s_frac 1 1 11289600 0
> i2s_pre 1 1 11289600 0
> sclk_i2s0 1 1 11289600 0
> i2s0_clkout 0 0 11289600 0
> hclk_i2s0 1 1 148500000 0
>
> "sclk_i2s0" is the master clock, should allow to set its parent's rate.
> Add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre" and "sclk_i2s0".
>
> Tested on rk3288 board using max98090, with command "aplay <music.wav>"
> and cat /sys/kernel/debug/clk/clk_summary |grep i2s
>
> Signed-off-by: Jianqun <jay.xu@rock-chips.com>
It looks like this is already in the mainline kernel [0].
It seems like I didn't catch the "Change-Id" at the time, and it is the
variant where i2s_clkout can set the parent rates.
Could you do a follow-up patch removing the CLK_SET_RATE_PARENT from
i2s_clkout again please?
Thanks
Heiko
[0]
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=fc69ed70c16a31d6a77ec47a30a9fe941f763f1e
> ---
> change since v1:
> - no "Change-Id"s in upstream patches, suggested by Heiko
> - to limit i2s0_clkout to select between its two parent without being able
> influence the core i2s clock, suggested by Heiko
>
> drivers/clk/rockchip/clk-rk3288.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index b22a2d2..ae32d78 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -238,15 +238,15 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = { COMPOSITE(0, "i2s_src",
> mux_pll_src_cpll_gpll_p, 0,
> RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
> RK3288_CLKGATE_CON(4), 1, GFLAGS),
> - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
> + COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(8), 0,
> RK3288_CLKGATE_CON(4), 2, GFLAGS),
> - MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
> + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
> RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
> COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
> RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
> RK3288_CLKGATE_CON(4), 0, GFLAGS),
> - GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
> + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
> RK3288_CLKGATE_CON(4), 3, GFLAGS),
>
> MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
^ permalink raw reply [flat|nested] 7+ messages in thread