From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation
Date: Wed, 08 Jan 2014 14:09:11 +0100 [thread overview]
Message-ID: <14122384.i9DNmsOzpC@wuerfel> (raw)
In-Reply-To: <CAOQ7t2bg7qmwnQ-7iqbKCqK8fNS5GC=G0BN2188FQhPLN3v9VQ@mail.gmail.com>
On Wednesday 08 January 2014 12:49:10 Carlo Caione wrote:
> >> +sc-nmi-intc at 01c00030 {
> >> + compatible = "allwinner,sun7i-sc-nmi";
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + reg = <0x01c00030 0x0c>;
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <0 0 1>;
> >> +};
> >
> > Is <0 0 1> the correct representation of the NMI? This question has recently
> > come up on IRC and I didn't know the answer at the time.
>
> Why shouldn't it be a correct representation? I think I missed the
> discussion on IRC.
For all I know, the NMI and the IRQ input to the CPU are separate pins,
so the NMI irqchip is not actually cascaded to the GIC, and SPI-0
might in fact be a different interrupt source.
Arnd
next prev parent reply other threads:[~2014-01-08 13:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-06 17:41 [PATCH v2 0/3] ARM: sun7i: irqchip: Irqchip driver for NMI Carlo Caione
2014-01-06 17:41 ` [PATCH v2 1/3] ARM: sun7i: irqchip: Add irqchip driver for NMI controller Carlo Caione
2014-01-06 17:41 ` [PATCH v2 2/3] ARM: sun7i: dts: Add NMI irqchip support Carlo Caione
2014-01-06 17:41 ` [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation Carlo Caione
2014-01-08 11:29 ` Arnd Bergmann
2014-01-08 11:49 ` Carlo Caione
2014-01-08 13:03 ` Hans de Goede
2014-01-09 14:00 ` Carlo Caione
2014-01-08 13:09 ` Arnd Bergmann [this message]
2014-01-09 13:59 ` [linux-sunxi] " Carlo Caione
2014-01-09 14:37 ` Arnd Bergmann
2014-01-08 10:41 ` [PATCH v2 0/3] ARM: sun7i: irqchip: Irqchip driver for NMI Carlo Caione
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