[PATCH v2 0/2] init some clock rate from dts for rk3288

[PATCH v2 0/2] init some clock rate from dts for rk3288

[Kever Yang]

This patch add init rate for PLLs and some bus clock  from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
We need Doug's patch to make "aclk_cpu" get set properly:
	<https://patchwork.kernel.org/patch/5038781/>

Changes in v2:
- change the PLL setting of 400M to meet the constraints of TRM
- add review and test tag
- add some explanation in commit message

Kever Yang (2):
  clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
  ARM: dts: enable init rate for clock

 arch/arm/boot/dts/rk3288.dtsi     | 10 ++++++++++
 drivers/clk/rockchip/clk-rk3288.c |  2 ++
 2 files changed, 12 insertions(+)

-- 
1.9.1

[PATCH v2 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate

[Kever Yang]

This patch add 400MHz and 500MHz to clock rate table for rk3288.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v2:
- change the PLL setting of 400M to meet the constraints of TRM

 drivers/clk/rockchip/clk-rk3288.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index d053529..7c30a5a 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -86,8 +86,10 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
 	RK3066_PLL_RATE( 594000000, 2, 198, 4),
 	RK3066_PLL_RATE( 552000000, 1, 46, 2),
 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
+	RK3066_PLL_RATE( 500000000, 3, 125, 2),
 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
+	RK3066_PLL_RATE( 400000000, 3, 100, 2),
 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
-- 
1.9.1

[PATCH v2 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate

[Doug Anderson]

Kever

On Thu, Oct 9, 2014 at 9:50 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patch add 400MHz and 500MHz to clock rate table for rk3288.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - change the PLL setting of 400M to meet the constraints of TRM
>
>  drivers/clk/rockchip/clk-rk3288.c | 2 ++
>  1 file changed, 2 insertions(+)

Thanks!  These numbers for 400MHz look better.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH v2 2/2] ARM: dts: enable init rate for clock

[Kever Yang]

We need to initialize PLL rate and some of bus clock rate while
kernel init, for there is no other module will do that.

Basically on rk3288 we use GPLL for cpu bus, peripheral bus and
most of peripheral clock, CPLL for devices who require 50M/200M
clock rate, leave NPLL behind for special requirement from
display system.

The common-clock-framework will help us to select best source for
child clocks after we init the PLLs propriety.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
---

Changes in v2:
- add review and test tag
- add some explanation in commit message

 arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..2f4519b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -455,6 +455,16 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+				  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+				  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+				  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+				  <&cru PCLK_PERI>;
+		assigned-clock-rates = <594000000>, <400000000>,
+				       <500000000>, <300000000>,
+				       <150000000>, <75000000>,
+				       <300000000>, <150000000>,
+				       <75000000>;
 	};
 
 	grf: syscon at ff770000 {
-- 
1.9.1

[PATCH v2 0/2] init some clock rate from dts for rk3288

[Heiko Stübner]

Am Donnerstag, 9. Oktober 2014, 21:50:28 schrieb Kever Yang:
> This patch add init rate for PLLs and some bus clock  from dts for rk3288,
> add two clock rate of 400M and 500M into rate table for we will use it.
> We need Doug's patch to make "aclk_cpu" get set properly:
> 	<https://patchwork.kernel.org/patch/5038781/>
> 
> Changes in v2:
> - change the PLL setting of 400M to meet the constraints of TRM
> - add review and test tag
> - add some explanation in commit message
> 
> Kever Yang (2):
>   clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
>   ARM: dts: enable init rate for clock

I've added both patches to my wip branches for clock and dts.
I've also adapted the subject of the 2nd one to

	"ARM: dts: rockchip: enable init rate for clock"

because otherwise people reading the log won't be able to see which subarch 
this is.


Heiko

> 
>  arch/arm/boot/dts/rk3288.dtsi     | 10 ++++++++++
>  drivers/clk/rockchip/clk-rk3288.c |  2 ++
>  2 files changed, 12 insertions(+)