[RFC 0/3] ARM: sun9i: Add PRCM clocks and reset controls support

[RFC 0/3] ARM: sun9i: Add PRCM clocks and reset controls support

[Chen-Yu Tsai]

Hi,

This series adds basic support for the PRCM module on sun9i, which
has clock and reset controls for the CPU-S or RTC block.

The series is marked RFC, because we do not have actual documentation
for it. I am assuming the clock tree and register format is the same
as the A31 and A23. Obviously we will need to do some testing to verify,
which we would need actual peripherals to do.

I'm posting this so Maxime can test his pinctrl drivers, and then we
can work out how to verify the clocks.


Cheers
ChenYu


Chen-Yu Tsai (3):
  clk: sunxi: sun6i-apb0: Add support for sun9i A80 apbs gates
  mfd: sun6i-prcm: Add support for PRCM found on Allwinner A80 SoC
  ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes

 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 arch/arm/boot/dts/sun9i-a80.dtsi                  | 47 +++++++++++++++++++-
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c          |  6 +++
 drivers/mfd/sun6i-prcm.c                          | 52 +++++++++++++++++++++++
 4 files changed, 105 insertions(+), 1 deletion(-)

-- 
2.1.1

[RFC 1/3] clk: sunxi: sun6i-apb0: Add support for sun9i A80 apbs gates

[Chen-Yu Tsai]

This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

The gate bitmask is not complete. The lowest 7 bits seem to be the
same as found on the A31, judging by Allwinner's kernel sources and
what was enabled by the bootloader. Bits 17 and 18 are documented
in the SDK sources.

This still leaves some peripherals missing, such as the dma controller,
a second i2c controller, and 2 PS/2 controllers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c          | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0455cb9..15e44fa 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -56,6 +56,7 @@ Required properties:
 	"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
 	"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index e10d052..1e3d6c8 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -29,9 +29,15 @@ static const struct gates_data sun8i_a23_apb0_gates __initconst = {
 	.mask = {0x5D},
 };
 
+/* XXX This is an imcomplete mask due to a lack of documents */
+static const struct gates_data sun9i_a80_apbs_gates __initconst = {
+	.mask = {0x6007f},
+};
+
 static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
 	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
+	{ .compatible = "allwinner,sun9i-a80-apbs-gates-clk", .data = &sun9i_a80_apbs_gates },
 	{ /* sentinel */ }
 };
 
-- 
2.1.1

[RFC 2/3] mfd: sun6i-prcm: Add support for PRCM found on Allwinner A80 SoC

[Chen-Yu Tsai]

This patch adds support for the PRCM on the A80 SoC. There is little
to no document for this at the moment. Only register offsets are
available. However with some testing, the clock and reset controls
seem to be the similar to the ones on the A31.

One thing that needs verifying is whether the apbs divider is the same
as the A31 or the A23. The lowest divider is different between those
2 implementations.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mfd/sun6i-prcm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
index 283ab8d..4589acb 100644
--- a/drivers/mfd/sun6i-prcm.c
+++ b/drivers/mfd/sun6i-prcm.c
@@ -33,6 +33,22 @@ static const struct resource sun6i_a31_apb0_clk_res[] = {
 	},
 };
 
+static const struct resource sun9i_a80_cpus_clk_res[] = {
+	{
+		.start = 0x10,
+		.end = 0x13,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static const struct resource sun9i_a80_apbs_clk_res[] = {
+	{
+		.start = 0x1c,
+		.end = 0x1f,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
 static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	{
 		.start = 0x28,
@@ -97,6 +113,33 @@ static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
 	},
 };
 
+static const struct mfd_cell sun9i_a80_prcm_subdevs[] = {
+	{
+		.name = "sun6i-a31-ar100-clk",
+		.of_compatible = "allwinner,sun6i-a31-ar100-clk",
+		.num_resources = ARRAY_SIZE(sun9i_a80_cpus_clk_res),
+		.resources = sun9i_a80_cpus_clk_res,
+	},
+	{
+		.name = "sun8i-a23-apb0-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-clk",
+		.num_resources = ARRAY_SIZE(sun9i_a80_apbs_clk_res),
+		.resources = sun9i_a80_apbs_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-gates-clk",
+		.of_compatible = "allwinner,sun9i-a80-apbs-gates-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
+		.resources = sun6i_a31_apb0_gates_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-clock-reset",
+		.of_compatible = "allwinner,sun6i-a31-clock-reset",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
+		.resources = sun6i_a31_apb0_rstc_res,
+	},
+};
+
 static const struct prcm_data sun6i_a31_prcm_data = {
 	.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
 	.subdevs = sun6i_a31_prcm_subdevs,
@@ -107,6 +150,11 @@ static const struct prcm_data sun8i_a23_prcm_data = {
 	.subdevs = sun8i_a23_prcm_subdevs,
 };
 
+static const struct prcm_data sun9i_a80_prcm_data = {
+	.nsubdevs = ARRAY_SIZE(sun9i_a80_prcm_subdevs),
+	.subdevs = sun9i_a80_prcm_subdevs,
+};
+
 static const struct of_device_id sun6i_prcm_dt_ids[] = {
 	{
 		.compatible = "allwinner,sun6i-a31-prcm",
@@ -116,6 +164,10 @@ static const struct of_device_id sun6i_prcm_dt_ids[] = {
 		.compatible = "allwinner,sun8i-a23-prcm",
 		.data = &sun8i_a23_prcm_data,
 	},
+	{
+		.compatible = "allwinner,sun9i-a80-prcm",
+		.data = &sun9i_a80_prcm_data,
+	},
 	{ /* sentinel */ },
 };
 
-- 
2.1.1

[RFC 3/3] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes

[Chen-Yu Tsai]

This adds the PRCM clocks and reset controls to the A80 dtsi.

The list of apbs clock gates is incomplete. Tests show that bits 0~20
are mutable. We will need documents from Allwinner to complete the
support.

Also update clock and reset phandles for r_uart.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 47 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 2a1c10d..1f3da34 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -418,13 +418,58 @@
 			interrupts = <0 36 4>;
 		};
 
+		prcm at 08001400 {
+			compatible = "allwinner,sun9i-a80-prcm";
+			reg = <0x08001400 0x200>;
+
+			cpus_clk: cpus_clk {
+				compatible = "allwinner,sun6i-a31-ar100-clk";
+				#clock-cells = <0>;
+				clocks = <&osc32k>, <&osc24M>, <&pll4>;
+				clock-output-names = "cpus";
+			};
+
+			ahbs: ahbs_clk {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+				clocks = <&cpus_clk>;
+				clock-output-names = "ahbs";
+			};
+
+			apbs: apbs_clk {
+				compatible = "allwinner,sun8i-a23-apb0-clk";
+				#clock-cells = <0>;
+				clocks = <&ahbs>;
+				clock-output-names = "apbs";
+			};
+
+			apbs_gates: apbs_gates_clk {
+				compatible = "allwinner,sun9i-a80-apbs-gates-clk";
+				#clock-cells = <1>;
+				clocks = <&apbs>;
+				clock-output-names = "apbs_pio", "apbs_ir",
+						"apbs_timer", "apbs_rsb",
+						"apbs_uart", "apbs_1wire",
+						"apbs_i2c", "apbs_i2s0",
+						"apbs_i2s1";
+			};
+
+			apbs_rst: apbs_rst {
+				compatible = "allwinner,sun6i-a31-clock-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		r_uart: serial at 08002800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x08002800 0x400>;
 			interrupts = <0 38 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&apbs_gates 4>;
+			resets = <&apbs_rst 4>;
 			status = "disabled";
 		};
 	};
-- 
2.1.1

[RFC 0/3] ARM: sun9i: Add PRCM clocks and reset controls support

[Maxime Ripard]

Hi Chen-Yu,

On Tue, Oct 21, 2014 at 02:49:24PM +0800, Chen-Yu Tsai wrote:
> This series adds basic support for the PRCM module on sun9i, which
> has clock and reset controls for the CPU-S or RTC block.
> 
> The series is marked RFC, because we do not have actual documentation
> for it. I am assuming the clock tree and register format is the same
> as the A31 and A23. Obviously we will need to do some testing to verify,
> which we would need actual peripherals to do.
> 
> I'm posting this so Maxime can test his pinctrl drivers, and then we
> can work out how to verify the clocks.

This looks fine overall, but I'm a bit worried that there is too much
that we don't really know about in this.

Do we need it right now, or can it wait for some A80 documents to be
released? Maybe we can just postpone this until we have more
informations on this if it's not going to be used anytime soon anyway.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 0/3] ARM: sun9i: Add PRCM clocks and reset controls support

[Chen-Yu Tsai]

Hi,

On Wed, Oct 29, 2014 at 5:10 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Tue, Oct 21, 2014 at 02:49:24PM +0800, Chen-Yu Tsai wrote:
>> This series adds basic support for the PRCM module on sun9i, which
>> has clock and reset controls for the CPU-S or RTC block.
>>
>> The series is marked RFC, because we do not have actual documentation
>> for it. I am assuming the clock tree and register format is the same
>> as the A31 and A23. Obviously we will need to do some testing to verify,
>> which we would need actual peripherals to do.
>>
>> I'm posting this so Maxime can test his pinctrl drivers, and then we
>> can work out how to verify the clocks.
>
> This looks fine overall, but I'm a bit worried that there is too much
> that we don't really know about in this.
>
> Do we need it right now, or can it wait for some A80 documents to be
> released? Maybe we can just postpone this until we have more
> informations on this if it's not going to be used anytime soon anyway.

As I said, the main purpose of getting this out is for you to be able
to test R_PIO. The other reason for it would be for connecting the
AXP PMICs, which would either use I2C or Allwinner's RSB. Either way
we need both PRCM and R_PIO support to do any experimenting.

In short, this series is here so anyone wanting to work on said
peripherals will have something to work with.


Cheers
ChenYu