* [RESENDv6 1/6] ARM: dts: Add SoC level device tree support for LS1021A
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
@ 2014-10-31 9:01 ` Jingchang Lu
2014-10-31 9:01 ` [PATCHv7 2/6] ARM: dts: Add initial LS1021A QDS board dts support Jingchang Lu
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Jingchang Lu @ 2014-10-31 9:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
This add Freescale QorIQ LS1021A SoC device tree support.
The QorIQ LS1021A processor incorporates dual ARM Cortex-A7 cores,
providing virtualization support, advanced security features and the
broadest array of high-speed interconnects and optimized peripheral
features.
The LS1021A SoC shares IPs with i.MX, Vybrid and PowerPC platform.
For the detail information about Freescale QorIQ LS1021A SoC,
please refer to the QorIQ LS1021A Reference Manual.
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 408 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 408 insertions(+)
create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 0000000..657da14
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "fsl,ls1021a";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ serial4 = &lpuart4;
+ serial5 = &lpuart5;
+ sysclk = &sysclk;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at f00 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0xf00>;
+ clocks = <&cluster1_clk>;
+ };
+
+ cpu at f01 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0xf01>;
+ clocks = <&cluster1_clk>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ device_type = "soc";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0x0 0x1000>,
+ <0x0 0x1402000 0x0 0x1000>,
+ <0x0 0x1404000 0x0 0x2000>,
+ <0x0 0x1406000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+ };
+
+ ifc: ifc at 1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1021a-dcfg", "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ esdhc: esdhc at 1560000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1021a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
+
+ clockgen: clocking at 1ee1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1ee1000 0x10000>;
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "sysclk";
+ };
+
+ cga_pll1: pll at 800 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0x800 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "cga-pll1", "cga-pll1-div2",
+ "cga-pll1-div4";
+ };
+
+ platform_clk: pll at c00 {
+ compatible = "fsl,qoriq-core-pll-2.0";
+ #clock-cells = <1>;
+ reg = <0xc00 0x10>;
+ clocks = <&sysclk>;
+ clock-output-names = "platform-clk", "platform-clk-div2";
+ };
+
+ cluster1_clk: clk0c0 at 0 {
+ compatible = "fsl,qoriq-core-mux-2.0";
+ #clock-cells = <0>;
+ reg = <0x0 0x10>;
+ clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+ clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+ clock-output-names = "cluster1-clk";
+ };
+ };
+
+ dspi0: dspi at 2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&platform_clk 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi at 2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&platform_clk 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&platform_clk 1>;
+ status = "disabled";
+ };
+
+ uart0: serial at 21c0500 {
+ compatible = "fsl,16550-FIFO64", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <15>;
+ status = "disabled";
+ };
+
+ uart1: serial at 21c0600 {
+ compatible = "fsl,16550-FIFO64", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <15>;
+ status = "disabled";
+ };
+
+ uart2: serial at 21d0500 {
+ compatible = "fsl,16550-FIFO64", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <15>;
+ status = "disabled";
+ };
+
+ uart3: serial at 21d0600 {
+ compatible = "fsl,16550-FIFO64", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ fifo-size = <15>;
+ status = "disabled";
+ };
+
+ lpuart0: serial at 2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial at 2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial at 2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial at 2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial at 2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial at 29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ wdog0: watchdog at 2ad0000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "wdog-en";
+ big-endian;
+ };
+
+ sai1: sai at 2b50000 {
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b50000 0x0 0x10000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "sai";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 47>,
+ <&edma0 1 46>;
+ big-endian;
+ status = "disabled";
+ };
+
+ sai2: sai at 2b60000 {
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b60000 0x0 0x10000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ clock-names = "sai";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 45>,
+ <&edma0 1 44>;
+ big-endian;
+ status = "disabled";
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&platform_clk 1>,
+ <&platform_clk 1>;
+ };
+
+ mdio0: mdio at 2d24000 {
+ compatible = "gianfar";
+ device_type = "mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2d24000 0x0 0x4000>;
+ };
+
+ usb at 8600000 {
+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+ reg = <0x0 0x8600000 0x0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
+
+ usb3 at 3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ };
+ };
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCHv7 2/6] ARM: dts: Add initial LS1021A QDS board dts support
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
2014-10-31 9:01 ` [RESENDv6 1/6] ARM: dts: Add SoC level device tree support for LS1021A Jingchang Lu
@ 2014-10-31 9:01 ` Jingchang Lu
2014-10-31 9:01 ` [PATCHv7 3/6] ARM: dts: Add initial LS1021A TWR " Jingchang Lu
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Jingchang Lu @ 2014-10-31 9:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
The LS1021A QorIQ development system (QDS) is a high-performance
computing evaluation, development and test platform supporting
the LS1021A processor. The LS1021A QDS is optimized to support
the high-bandwidth DDR3LP/DDR4 memory and a full complement of
high-speed SerDes ports.
For more detail information about the LS1021AQDS, please refer to
the QorIQ LS1021A Development System Reference Manual.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/ls1021a-qds.dts | 240 ++++++++++++++++++++++++++++++++++++++
2 files changed, 241 insertions(+)
create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 472c1c3..515ce04 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -251,6 +251,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-tx6q-1110.dtb \
imx6sl-evk.dtb \
imx6sx-sdb.dtb \
+ ls1021a-qds.dtb \
vf610-colibri-eval-v3.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 0000000..9c5e16b
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A QDS Board";
+
+ aliases {
+ enet0_rgmii_phy = &rgmii_phy1;
+ enet1_rgmii_phy = &rgmii_phy2;
+ enet2_rgmii_phy = &rgmii_phy3;
+ enet0_sgmii_phy = &sgmii_phy1c;
+ enet1_sgmii_phy = &sgmii_phy1d;
+ };
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: at45db021d at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9547: mux at 77 {
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ ds3232: rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220 at 40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220 at 41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom at 56 {
+ compatible = "atmel,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom at 57 {
+ compatible = "atmel,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a at 4c {
+ compatible = "adi,adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ status = "okay";
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ fpga: board-control at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ reg = <0x3 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 3 0 0x100>;
+
+ mdio-mux-emi1 {
+ compatible = "mdio-mux-mmioreg";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1[2:0] */
+
+ /* Onboard PHYs */
+ ls1021amdio0: mdio at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rgmii_phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+
+ ls1021amdio1: mdio at 20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rgmii_phy2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+ };
+
+ ls1021amdio2: mdio at 40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rgmii_phy3: ethernet-phy at 3 {
+ reg = <0x3>;
+ };
+ };
+
+ ls1021amdio3: mdio at 60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sgmii_phy1c: ethernet-phy at 1c {
+ reg = <0x1c>;
+ };
+ };
+
+ ls1021amdio4: mdio at 80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sgmii_phy1d: ethernet-phy at 1d {
+ reg = <0x1d>;
+ };
+ };
+ };
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ tbi0: tbi-phy at 8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCHv7 3/6] ARM: dts: Add initial LS1021A TWR board dts support
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
2014-10-31 9:01 ` [RESENDv6 1/6] ARM: dts: Add SoC level device tree support for LS1021A Jingchang Lu
2014-10-31 9:01 ` [PATCHv7 2/6] ARM: dts: Add initial LS1021A QDS board dts support Jingchang Lu
@ 2014-10-31 9:01 ` Jingchang Lu
2014-10-31 9:01 ` [RESENDv5 4/6] dt-bindings: arm: add Freescale LS1021A SoC device tree binding Jingchang Lu
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Jingchang Lu @ 2014-10-31 9:01 UTC (permalink / raw)
To: linux-arm-kernel
The LS1021A TWR is a low cost, high-performance evaluation,
development and test platform supporting the LS1021A processor.
It is optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
For more detail information about the LS1021A TWR board, please
refer to LS1021A QorIQ Tower System Reference Manual.
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/ls1021a-twr.dts | 127 ++++++++++++++++++++++++++++++++++++++
2 files changed, 128 insertions(+)
create mode 100644 arch/arm/boot/dts/ls1021a-twr.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 515ce04..cdb561c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -252,6 +252,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6sl-evk.dtb \
imx6sx-sdb.dtb \
ls1021a-qds.dtb \
+ ls1021a-twr.dtb \
vf610-colibri-eval-v3.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100644
index 0000000..a2c591e
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A TWR Board";
+
+ aliases {
+ enet2_rgmii_phy = &rgmii_phy1;
+ enet0_sgmii_phy = &sgmii_phy2;
+ enet1_sgmii_phy = &sgmii_phy0;
+ };
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: s25fl064k at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl064k";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR Flash on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
+ status = "okay";
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ sgmii_phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ rgmii_phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ sgmii_phy2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+ tbi1: tbi-phy at 1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [RESENDv5 4/6] dt-bindings: arm: add Freescale LS1021A SoC device tree binding
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
` (2 preceding siblings ...)
2014-10-31 9:01 ` [PATCHv7 3/6] ARM: dts: Add initial LS1021A TWR " Jingchang Lu
@ 2014-10-31 9:01 ` Jingchang Lu
2014-10-31 9:01 ` [RESENDv5 5/6] ARM: imx: Add initial support for Freescale LS1021A Jingchang Lu
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Jingchang Lu @ 2014-10-31 9:01 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
Documentation/devicetree/bindings/arm/fsl.txt | 38 +++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index e935d7d..4e8b7df 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -74,3 +74,41 @@ Required root node properties:
i.MX6q generic board
Required root node properties:
- compatible = "fsl,imx6q";
+
+
+Freescale LS1021A Platform Device Tree Bindings
+------------------------------------------------
+
+Required root node compatible properties:
+ - compatible = "fsl,ls1021a";
+
+Freescale LS1021A SoC-specific Device Tree Bindings
+-------------------------------------------
+
+Freescale SCFG
+ SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+ Required properties:
+ - compatible: should be "fsl,ls1021a-scfg"
+ - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1021a-scfg";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
+
+Freescale DCFG
+ DCFG is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+ Required properties:
+ - compatible: should be "fsl,ls1021a-dcfg"
+ - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1021a-dcfg";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [RESENDv5 5/6] ARM: imx: Add initial support for Freescale LS1021A
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
` (3 preceding siblings ...)
2014-10-31 9:01 ` [RESENDv5 4/6] dt-bindings: arm: add Freescale LS1021A SoC device tree binding Jingchang Lu
@ 2014-10-31 9:01 ` Jingchang Lu
2014-11-11 16:03 ` [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A Arnd Bergmann
2014-10-31 9:01 ` [RESENDv6 6/6] ARM: imx: Add Freescale LS1021A SMP support Jingchang Lu
2014-11-04 5:28 ` [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Shawn Guo
6 siblings, 1 reply; 13+ messages in thread
From: Jingchang Lu @ 2014-10-31 9:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
The LS1021A SoC is a dual-core Cortex-A7 based processor,
this adds the initial support for it.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
arch/arm/mach-imx/Kconfig | 14 ++++++++++++++
arch/arm/mach-imx/Makefile | 2 ++
arch/arm/mach-imx/mach-ls1021a.c | 21 +++++++++++++++++++++
3 files changed, 37 insertions(+)
create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e26b0fd..ef549ef 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -658,6 +658,20 @@ choice
endchoice
+config FSL_SOC
+ bool
+
+config SOC_LS1021A
+ bool "Freescale LS1021A support"
+ select ARM_GIC
+ select HAVE_ARM_ARCH_TIMER
+ select FSL_SOC
+ select PCI_DOMAINS if PCI
+ select ZONE_DMA if ARM_LPAE
+
+ help
+ This enable support for Freescale LS1021A processor.
+
endif
source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b8580f3..19dc7bf 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+
obj-y += devices/
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 0000000..9d2034b
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const ls1021a_dt_compat[] __initconst = {
+ "fsl,ls1021a",
+ NULL,
+};
+
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+ .dt_compat = ls1021a_dt_compat,
+MACHINE_END
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
2014-10-31 9:01 ` [RESENDv5 5/6] ARM: imx: Add initial support for Freescale LS1021A Jingchang Lu
@ 2014-11-11 16:03 ` Arnd Bergmann
2014-11-12 10:42 ` Shawn Guo
0 siblings, 1 reply; 13+ messages in thread
From: Arnd Bergmann @ 2014-11-11 16:03 UTC (permalink / raw)
To: linux-arm-kernel
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which
is originally symbol used for the PowerPC based platforms
and guards lots of code that does not build on ARM.
This breaks allmodconfig, so let's remove it for now, until
either all those drivers are fixed or they use a dependency
on IMX instead.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
On Friday 31 October 2014 17:01:12 Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
>
> The LS1021A SoC is a dual-core Cortex-A7 based processor,
> this adds the initial support for it.
>
> Signed-off-by: Jingchang Lu <b35083@freescale.com>
>
> +config FSL_SOC
> + bool
> +
> +config SOC_LS1021A
> + bool "Freescale LS1021A support"
> + select ARM_GIC
> + select HAVE_ARM_ARCH_TIMER
> + select FSL_SOC
>
This broke allmodconfig builds in linux-next, please apply this
partial revert for the moment.
Arnd
---
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ef549ef1cd6d..e8627e04e1e6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -658,14 +658,10 @@ choice
endchoice
-config FSL_SOC
- bool
-
config SOC_LS1021A
bool "Freescale LS1021A support"
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
- select FSL_SOC
select PCI_DOMAINS if PCI
select ZONE_DMA if ARM_LPAE
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
2014-11-11 16:03 ` [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A Arnd Bergmann
@ 2014-11-12 10:42 ` Shawn Guo
2014-11-12 11:04 ` Arnd Bergmann
0 siblings, 1 reply; 13+ messages in thread
From: Shawn Guo @ 2014-11-12 10:42 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 11, 2014 at 05:03:25PM +0100, Arnd Bergmann wrote:
> The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which
> is originally symbol used for the PowerPC based platforms
> and guards lots of code that does not build on ARM.
>
> This breaks allmodconfig, so let's remove it for now, until
> either all those drivers are fixed or they use a dependency
> on IMX instead.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> ---
> On Friday 31 October 2014 17:01:12 Jingchang Lu wrote:
> > From: Jingchang Lu <b35083@freescale.com>
> >
> > The LS1021A SoC is a dual-core Cortex-A7 based processor,
> > this adds the initial support for it.
> >
> > Signed-off-by: Jingchang Lu <b35083@freescale.com>
>
> >
> > +config FSL_SOC
> > + bool
> > +
> > +config SOC_LS1021A
> > + bool "Freescale LS1021A support"
> > + select ARM_GIC
> > + select HAVE_ARM_ARCH_TIMER
> > + select FSL_SOC
> >
>
>
> This broke allmodconfig builds in linux-next, please apply this
> partial revert for the moment.
I noticed the issue from 0-DAY testing and was trying to drop the patch.
Jingchang said someone is trying to fixing the issues from driver code.
But it seems to take some time. So I agree with this partial reverting.
Patch applied. Thanks Arnd.
Shawn
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index ef549ef1cd6d..e8627e04e1e6 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -658,14 +658,10 @@ choice
>
> endchoice
>
> -config FSL_SOC
> - bool
> -
> config SOC_LS1021A
> bool "Freescale LS1021A support"
> select ARM_GIC
> select HAVE_ARM_ARCH_TIMER
> - select FSL_SOC
> select PCI_DOMAINS if PCI
> select ZONE_DMA if ARM_LPAE
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
2014-11-12 10:42 ` Shawn Guo
@ 2014-11-12 11:04 ` Arnd Bergmann
2014-11-14 9:31 ` Jingchang Lu
0 siblings, 1 reply; 13+ messages in thread
From: Arnd Bergmann @ 2014-11-12 11:04 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 12 November 2014 18:42:41 Shawn Guo wrote:
>
> I noticed the issue from 0-DAY testing and was trying to drop the patch.
> Jingchang said someone is trying to fixing the issues from driver code.
> But it seems to take some time. So I agree with this partial reverting.
>
> Patch applied. Thanks Arnd.
Thanks a lot!
Jingchang, can you say which of the drivers that are currently depending
on FSL_SOC are reused on LS1021A? I see these ones in the source tree:
drivers/ata/sata_fsl.c
drivers/crypto/caam/
drivers/crypto/talitos.c
drivers/dma/fsldma.c
drivers/memory/fsl_ifc.c
drivers/misc/carma/
drivers/mtd/nand/fsl_ifc_nand.c
drivers/net/ethernet/freescale/fsl_pq_mdio.c
drivers/net/ethernet/freescale/gianfar*
drivers/net/ethernet/freescale/xgmac_mdio.c
drivers/spi/spi-fsl-cpm.c
drivers/spi/spi-fsl-dspi.c
drivers/spi/spi-fsl-espi.c
drivers/usb/host/ehci-fsl.c
drivers/video/fbdev/fsl-diu-fb.c
drivers/virt/fsl_hypervisor.c
sound/soc/fsl/mpc*
I suspect that you only want a small subset of these, but I have no idea
which.
Arnd
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
2014-11-12 11:04 ` Arnd Bergmann
@ 2014-11-14 9:31 ` Jingchang Lu
2014-11-14 10:56 ` Arnd Bergmann
0 siblings, 1 reply; 13+ messages in thread
From: Jingchang Lu @ 2014-11-14 9:31 UTC (permalink / raw)
To: linux-arm-kernel
>-----Original Message-----
>From: Arnd Bergmann [mailto:arnd at arndb.de]
>Sent: Wednesday, November 12, 2014 7:05 PM
>To: linux-arm-kernel at lists.infradead.org
>Cc: Shawn Guo; mark.rutland at arm.com; devicetree at vger.kernel.org; Lu
>Jingchang-B35083
>Subject: Re: [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from
>LS1021A
>
>On Wednesday 12 November 2014 18:42:41 Shawn Guo wrote:
>>
>> I noticed the issue from 0-DAY testing and was trying to drop the patch.
>> Jingchang said someone is trying to fixing the issues from driver code.
>> But it seems to take some time. So I agree with this partial reverting.
>>
>> Patch applied. Thanks Arnd.
>
>Thanks a lot!
>
>Jingchang, can you say which of the drivers that are currently depending
>on FSL_SOC are reused on LS1021A? I see these ones in the source tree:
>
>drivers/ata/sata_fsl.c
>drivers/crypto/caam/
>drivers/crypto/talitos.c
>drivers/dma/fsldma.c
>drivers/memory/fsl_ifc.c
>drivers/misc/carma/
>drivers/mtd/nand/fsl_ifc_nand.c
>drivers/net/ethernet/freescale/fsl_pq_mdio.c
>drivers/net/ethernet/freescale/gianfar*
>drivers/net/ethernet/freescale/xgmac_mdio.c
>drivers/spi/spi-fsl-cpm.c
>drivers/spi/spi-fsl-dspi.c
>drivers/spi/spi-fsl-espi.c
>drivers/usb/host/ehci-fsl.c
>drivers/video/fbdev/fsl-diu-fb.c
>drivers/virt/fsl_hypervisor.c
>sound/soc/fsl/mpc*
>
>I suspect that you only want a small subset of these, but I have no idea
>which.
>
> Arnd
Hi, Arnd and Shawn,
Many thanks for your work on resolving the FSL_SOC breaking allmodconfig.
Formerly many drivers on PPC depend on a FSL_SOC configuration, when they
are shared on our ARM platform, I add this configuration internally for
quick reference and also some internal developers' requirement, thus I
also add it into my upstream code.
Yes, only a subset of these drivers are shared between our ARM and PPC
platforms. Since there will be allmodconfig breaking fault due to the
FSL_SOC configuration, we will try to fix this or select another dependency,
I will also inform our driver owners about this.
Below drivers are shared on LS1021A platform currently:
drivers/crypto/caam/
drivers/memory/fsl_ifc.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/net/ethernet/freescale/fsl_pq_mdio.c
drivers/net/ethernet/freescale/gianfar*
drivers/spi/spi-fsl-dspi.c
Thanks and Best Regards,
Jingchang
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
2014-11-14 9:31 ` Jingchang Lu
@ 2014-11-14 10:56 ` Arnd Bergmann
0 siblings, 0 replies; 13+ messages in thread
From: Arnd Bergmann @ 2014-11-14 10:56 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 14 November 2014 09:31:42 Jingchang Lu wrote:
> Yes, only a subset of these drivers are shared between our ARM and PPC
> platforms. Since there will be allmodconfig breaking fault due to the
> FSL_SOC configuration, we will try to fix this or select another dependency,
> I will also inform our driver owners about this.
>
> Below drivers are shared on LS1021A platform currently:
>
> drivers/crypto/caam/
> drivers/memory/fsl_ifc.c
> drivers/mtd/nand/fsl_ifc_nand.c
> drivers/net/ethernet/freescale/fsl_pq_mdio.c
> drivers/net/ethernet/freescale/gianfar*
> drivers/spi/spi-fsl-dspi.c
Ok, since this is only a small subset of the FSL_SOC drivers, I'd
suggest you make these depend on (FSL_SOC || ARCH_IMX) after
verifying that they build without warnings on ARM.
Arnd
^ permalink raw reply [flat|nested] 13+ messages in thread
* [RESENDv6 6/6] ARM: imx: Add Freescale LS1021A SMP support
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
` (4 preceding siblings ...)
2014-10-31 9:01 ` [RESENDv5 5/6] ARM: imx: Add initial support for Freescale LS1021A Jingchang Lu
@ 2014-10-31 9:01 ` Jingchang Lu
2014-11-04 5:28 ` [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Shawn Guo
6 siblings, 0 replies; 13+ messages in thread
From: Jingchang Lu @ 2014-10-31 9:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingchang Lu <b35083@freescale.com>
Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-ls1021a.c | 1 +
arch/arm/mach-imx/platsmp.c | 33 +++++++++++++++++++++++++++++++++
4 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 19dc7bf..f5ac685 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 23c84e6..fe9a908 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -158,5 +158,6 @@ static inline void imx_init_l2cache(void) {}
#endif
extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
#endif
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index 9d2034b..b89c858 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[] __initconst = {
};
DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+ .smp = smp_ops(ls1021a_smp_ops),
.dt_compat = ls1021a_dt_compat,
MACHINE_END
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 771bd25..7f27001 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -11,7 +11,10 @@
*/
#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
#include <linux/smp.h>
+
#include <asm/cacheflush.h>
#include <asm/page.h>
#include <asm/smp_scu.h>
@@ -94,3 +97,33 @@ struct smp_operations imx_smp_ops __initdata = {
.cpu_kill = imx_cpu_kill,
#endif
};
+
+#define DCFG_CCSR_SCRATCHRW1 0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *np;
+ void __iomem *dcfg_base;
+ unsigned long paddr;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+ dcfg_base = of_iomap(np, 0);
+ BUG_ON(!dcfg_base);
+
+ paddr = virt_to_phys(secondary_startup);
+ writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+
+ iounmap(dcfg_base);
+}
+
+struct smp_operations ls1021a_smp_ops __initdata = {
+ .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
+ .smp_boot_secondary = ls1021a_boot_secondary,
+};
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support
2014-10-31 9:01 [PATCHv7 0/6] ARM: imx: Add Freescale LS1021A SoC and board support Jingchang Lu
` (5 preceding siblings ...)
2014-10-31 9:01 ` [RESENDv6 6/6] ARM: imx: Add Freescale LS1021A SMP support Jingchang Lu
@ 2014-11-04 5:28 ` Shawn Guo
6 siblings, 0 replies; 13+ messages in thread
From: Shawn Guo @ 2014-11-04 5:28 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Oct 31, 2014 at 05:01:07PM +0800, Jingchang Lu wrote:
> Jingchang Lu (6):
> ARM: dts: Add SoC level device tree support for LS1021A
> ARM: dts: Add initial LS1021A QDS board dts support
> ARM: dts: Add initial LS1021A TWR board dts support
> dt-bindings: arm: add Freescale LS1021A SoC device tree binding
> ARM: imx: Add initial support for Freescale LS1021A
> ARM: imx: Add Freescale LS1021A SMP support
Applied all, thanks.
^ permalink raw reply [flat|nested] 13+ messages in thread