From: jiang.liu@linux.intel.com (Jiang Liu)
To: linux-arm-kernel@lists.infradead.org
Subject: [Patch Part2 v4 27/31] x86, irq: Clean up unused MSI related code and interfaces
Date: Tue, 4 Nov 2014 20:02:01 +0800 [thread overview]
Message-ID: <1415102525-9898-28-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1415102525-9898-1-git-send-email-jiang.liu@linux.intel.com>
Now MSI interrupt has been converted to new hierarchy irqdomain
interfaces, so kill legacy MSI related code and interfaces.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
---
arch/x86/include/asm/hpet.h | 9 ------
arch/x86/include/asm/x86_init.h | 4 ---
arch/x86/kernel/apic/msi.c | 61 +++++----------------------------------
3 files changed, 7 insertions(+), 67 deletions(-)
diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h
index e87e9faf87a9..5fa9fb0f8809 100644
--- a/arch/x86/include/asm/hpet.h
+++ b/arch/x86/include/asm/hpet.h
@@ -85,15 +85,6 @@ extern struct irq_domain *hpet_create_irq_domain(int hpet_id);
extern int hpet_assign_irq(struct irq_domain *domain,
struct hpet_dev *dev, int dev_num);
-#ifdef CONFIG_PCI_MSI
-extern int default_setup_hpet_msi(unsigned int irq, unsigned int id);
-#else
-static inline int default_setup_hpet_msi(unsigned int irq, unsigned int id)
-{
- return -EINVAL;
-}
-#endif
-
#ifdef CONFIG_HPET_EMULATE_RTC
#include <linux/interrupt.h>
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index e45e4da96bf1..9b53cb2acfbb 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -176,13 +176,9 @@ struct msi_desc;
struct x86_msi_ops {
int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
- void (*compose_msi_msg)(struct pci_dev *dev, unsigned int irq,
- unsigned int dest, struct msi_msg *msg,
- u8 hpet_id);
void (*teardown_msi_irq)(unsigned int irq);
void (*teardown_msi_irqs)(struct pci_dev *dev);
void (*restore_msi_irqs)(struct pci_dev *dev);
- int (*setup_hpet_msi)(unsigned int irq, unsigned int id);
u32 (*msi_mask_irq)(struct msi_desc *desc, u32 mask, u32 flag);
u32 (*msix_mask_irq)(struct msi_desc *desc, u32 flag);
};
diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
index 265178b30816..6bfe85e96c74 100644
--- a/arch/x86/kernel/apic/msi.c
+++ b/arch/x86/kernel/apic/msi.c
@@ -25,16 +25,12 @@
static struct irq_domain *msi_default_domain;
-void native_compose_msi_msg(struct pci_dev *pdev,
- unsigned int irq, unsigned int dest,
- struct msi_msg *msg, u8 hpet_id)
+static void native_compose_msi_msg(struct irq_cfg *cfg, struct msi_msg *msg)
{
- struct irq_cfg *cfg = irq_cfg(irq);
-
msg->address_hi = MSI_ADDR_BASE_HI;
if (x2apic_enabled())
- msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
+ msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
msg->address_lo =
MSI_ADDR_BASE_LO |
@@ -44,7 +40,7 @@ void native_compose_msi_msg(struct pci_dev *pdev,
((apic->irq_delivery_mode != dest_LowestPrio) ?
MSI_ADDR_REDIRECTION_CPU :
MSI_ADDR_REDIRECTION_LOWPRI) |
- MSI_ADDR_DEST_ID(dest);
+ MSI_ADDR_DEST_ID(cfg->dest_apicid);
msg->data =
MSI_DATA_TRIGGER_EDGE |
@@ -55,7 +51,7 @@ void native_compose_msi_msg(struct pci_dev *pdev,
MSI_DATA_VECTOR(cfg->vector);
}
-static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+static void msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
struct irq_cfg *cfg = irqd_cfg(data);
@@ -93,31 +89,6 @@ static void msi_update_msg(struct msi_msg *msg, struct irq_data *irq_data)
msg->address_lo |= MSI_ADDR_DEST_ID(cfg->dest_apicid);
}
-static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
- struct msi_msg *msg, u8 hpet_id)
-{
- struct irq_cfg *cfg;
- int err;
- unsigned dest;
-
- if (disable_apic)
- return -ENXIO;
-
- cfg = irq_cfg(irq);
- err = assign_irq_vector(irq, cfg, apic->target_cpus());
- if (err)
- return err;
-
- err = apic->cpu_mask_to_apicid_and(cfg->domain,
- apic->target_cpus(), &dest);
- if (err)
- return err;
-
- x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
-
- return 0;
-}
-
static int msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
bool force)
{
@@ -148,7 +119,7 @@ struct irq_chip msi_chip = {
.irq_set_affinity = msi_set_affinity,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_print_chip = irq_remapping_print_chip,
- .irq_compose_msi_msg = irq_msi_compose_msg,
+ .irq_compose_msi_msg = msi_compose_msg,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
@@ -253,7 +224,7 @@ int arch_setup_dmar_msi(unsigned int irq)
struct msi_msg msg;
struct irq_cfg *cfg = irq_cfg(irq);
- native_compose_msi_msg(NULL, irq, cfg->dest_apicid, &msg, -1);
+ native_compose_msi_msg(cfg, &msg);
dmar_msi_write(irq, &msg);
irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
"edge");
@@ -305,28 +276,10 @@ static struct irq_chip hpet_msi_type = {
.irq_set_affinity = hpet_msi_set_affinity,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_print_chip = irq_remapping_print_chip,
- .irq_compose_msi_msg = irq_msi_compose_msg,
+ .irq_compose_msi_msg = msi_compose_msg,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
-int default_setup_hpet_msi(unsigned int irq, unsigned int id)
-{
- struct irq_chip *chip = &hpet_msi_type;
- struct msi_msg msg;
- int ret;
-
- ret = msi_compose_msg(NULL, irq, &msg, id);
- if (ret < 0)
- return ret;
-
- hpet_msi_write(irq_get_handler_data(irq), &msg);
- irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
- setup_remapped_irq(irq, irq_cfg(irq), chip);
-
- irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
- return 0;
-}
-
static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
--
1.7.10.4
next prev parent reply other threads:[~2014-11-04 12:02 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-04 12:01 [Patch Part2 v4 00/31] Enable hierarchy irqdomian on x86 platforms Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 01/31] irqdomain: Introduce new interfaces to support hierarchy irqdomains Jiang Liu
2014-11-05 23:48 ` Thomas Gleixner
2014-11-06 6:09 ` Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 02/31] irqdomain: Do irq_find_mapping and set_type for hierarchy irqdomain in case OF Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 03/31] genirq: Introduce helper functions to support stacked irq_chip Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 04/31] genirq: Introduce irq_chip.irq_compose_msi_msg() to support stacked irqchip Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 05/31] genirq: Add IRQ_SET_MASK_OK_DONE " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 06/31] x86, irq: Save destination CPU ID in irq_cfg Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 07/31] x86, irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 08/31] x86, hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 09/31] x86, MSI: " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 10/31] x86, uv: " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 11/31] x86, htirq: " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 12/31] x86, dmar: " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 13/31] x86: irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2014-11-06 11:43 ` Yijing Wang
2014-11-04 12:01 ` [Patch Part2 v4 14/31] iommu/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 15/31] iommu/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 16/31] iommu/amd: Enhance AMD " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 17/31] x86, hpet: Enhance HPET IRQ to support " Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 18/31] PCI/MSI, trivial: Fix minor syntax issues according to coding styles Jiang Liu
2014-11-05 22:10 ` Bjorn Helgaas
2014-11-05 22:10 ` Bjorn Helgaas
2014-11-04 12:01 ` [Patch Part2 v4 19/31] PCI/MSI: Simplify PCI MSI code by initializing msi_desc.nvec_used earlier Jiang Liu
2014-11-05 22:35 ` Bjorn Helgaas
2014-11-04 12:01 ` [Patch Part2 v4 20/31] PCI/MSI: Kill redundant calling for irq_set_msi_desc() for MSIx interrupts Jiang Liu
2014-11-05 22:45 ` Bjorn Helgaas
2014-11-06 1:32 ` Yijing Wang
2014-11-06 4:04 ` Bjorn Helgaas
2014-11-06 4:31 ` Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 21/31] PCI/MSI: enhance PCI MSI core to support hierarchy irqdomain Jiang Liu
2014-11-05 23:09 ` Bjorn Helgaas
2014-11-06 1:58 ` Yijing Wang
2014-11-06 4:10 ` Bjorn Helgaas
2014-11-06 4:54 ` Yijing Wang
2014-11-06 5:06 ` Jiang Liu
2014-11-06 5:42 ` Yijing Wang
2014-11-06 4:58 ` Jiang Liu
2014-11-06 5:28 ` Bjorn Helgaas
2014-11-06 10:01 ` Thomas Gleixner
2014-11-06 10:30 ` Thomas Gleixner
2014-11-06 11:41 ` Jiang Liu
2014-11-06 11:59 ` Thomas Gleixner
2014-11-04 12:01 ` [Patch Part2 v4 22/31] x86, PCI, MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 23/31] x86, irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 24/31] iommu/vt-d: Clean up unused MSI related code Jiang Liu
2014-11-04 12:01 ` [Patch Part2 v4 25/31] iommu/amd: " Jiang Liu
2014-11-04 12:02 ` [Patch Part2 v4 26/31] x86: irq_remapping: " Jiang Liu
2014-11-04 12:02 ` Jiang Liu [this message]
2014-11-04 12:02 ` [Patch Part2 v4 28/31] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2014-11-04 12:02 ` [Patch Part2 v4 29/31] x86, irq: Use hierarchy irqdomain to manage DMAR interrupts Jiang Liu
2014-11-04 12:02 ` [Patch Part2 v4 30/31] x86, htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2014-11-04 12:02 ` [Patch Part2 v4 31/31] x86, uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
2014-11-04 14:47 ` [Patch Part2 v4 00/31] Enable hierarchy irqdomian on x86 platforms Joerg Roedel
2014-11-04 15:12 ` Jiang Liu
2014-11-04 15:32 ` Joerg Roedel
2014-11-05 8:51 ` Joerg Roedel
2014-11-05 9:04 ` Jiang Liu
2014-11-05 9:41 ` Jiang Liu
2014-11-05 9:58 ` Joerg Roedel
2014-11-05 10:28 ` Jiang Liu
2014-11-05 11:10 ` Joerg Roedel
2014-11-06 13:07 ` Joerg Roedel
2014-11-06 13:35 ` Jiang Liu
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