From: jszhang@marvell.com (Jisheng Zhang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] irqchip: dw-apb-ictl: add PM support
Date: Wed, 12 Nov 2014 14:22:54 +0800 [thread overview]
Message-ID: <1415773374-4629-4-git-send-email-jszhang@marvell.com> (raw)
In-Reply-To: <1415773374-4629-1-git-send-email-jszhang@marvell.com>
This patch adds in support for S2R for dw-apb-ictl irqchip driver.
We can used relaxed variants in the resume hook because there's no DMA
at all here, the device type memory attribute can ensure the operations
order and relaxed version imply compiler barrier.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/irqchip/irq-dw-apb-ictl.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
index c136b67..53bb732 100644
--- a/drivers/irqchip/irq-dw-apb-ictl.c
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -50,6 +50,21 @@ static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+#ifdef CONFIG_PM
+static void dw_apb_ictl_resume(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct irq_chip_type *ct = irq_data_get_chip_type(d);
+
+ irq_gc_lock(gc);
+ writel_relaxed(~0, gc->reg_base + ct->regs.enable);
+ writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
+ irq_gc_unlock(gc);
+}
+#else
+#define dw_apb_ictl_resume NULL
+#endif /* CONFIG_PM */
+
static int __init dw_apb_ictl_init(struct device_node *np,
struct device_node *parent)
{
@@ -127,13 +142,17 @@ static int __init dw_apb_ictl_init(struct device_node *np,
gc->reg_base = iobase;
gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+ gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
if (nrirqs > 32) {
gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+ gc->chip_types[1].regs.enable = APB_INT_ENABLE_H;
gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+ gc->chip_types[1].chip.irq_resume = dw_apb_ictl_resume;
}
irq_set_handler_data(irq, gc);
--
2.1.3
next prev parent reply other threads:[~2014-11-12 6:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-12 6:22 [PATCH v2 0/3] irqchip: dw-apb-ictl: IRQ_GC_MASK_CACHE_PER_TYPE and PM support Jisheng Zhang
2014-11-12 6:22 ` [PATCH v2 1/3] irqchip: dw-apb-ictl: always use use {readl|writel}_relaxed Jisheng Zhang
2014-11-12 6:22 ` [PATCH v2 2/3] irqchip: dw-apb-ictl: enable IRQ_GC_MASK_CACHE_PER_TYPE Jisheng Zhang
2014-11-12 6:22 ` Jisheng Zhang [this message]
2014-11-26 8:20 ` [PATCH v2 0/3] irqchip: dw-apb-ictl: IRQ_GC_MASK_CACHE_PER_TYPE and PM support Jason Cooper
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