From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/4] clk: rockchip: setup pll_mux data earlier
Date: Thu, 20 Nov 2014 20:38:51 +0100 [thread overview]
Message-ID: <1416512333-15438-3-git-send-email-heiko@sntech.de> (raw)
In-Reply-To: <1416512333-15438-1-git-send-email-heiko@sntech.de>
In some cases we might need to access the data of the pll mux before the actual
mux gets registered - like in the following patch adding an init-callback.
Therefore populate pll_mux before registering the core pll-clock.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-pll.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index feb9cad..1bb6891 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -349,6 +349,19 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
pll->flags = clk_pll_flags;
pll->lock = lock;
+ /* create the mux on top of the real pll */
+ pll->pll_mux_ops = &clk_mux_ops;
+ pll_mux = &pll->pll_mux;
+ pll_mux->reg = base + mode_offset;
+ pll_mux->shift = mode_shift;
+ pll_mux->mask = PLL_MODE_MASK;
+ pll_mux->flags = 0;
+ pll_mux->lock = lock;
+ pll_mux->hw.init = &init;
+
+ if (pll_type == pll_rk3066)
+ pll_mux->flags |= CLK_MUX_HIWORD_MASK;
+
pll_clk = clk_register(NULL, &pll->hw);
if (IS_ERR(pll_clk)) {
pr_err("%s: failed to register pll clock %s : %ld\n",
@@ -357,10 +370,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
goto err_pll;
}
- /* create the mux on top of the real pll */
- pll->pll_mux_ops = &clk_mux_ops;
- pll_mux = &pll->pll_mux;
-
/* the actual muxing is xin24m, pll-output, xin32k */
pll_parents[0] = parent_names[0];
pll_parents[1] = pll_name;
@@ -372,16 +381,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
init.parent_names = pll_parents;
init.num_parents = ARRAY_SIZE(pll_parents);
- pll_mux->reg = base + mode_offset;
- pll_mux->shift = mode_shift;
- pll_mux->mask = PLL_MODE_MASK;
- pll_mux->flags = 0;
- pll_mux->lock = lock;
- pll_mux->hw.init = &init;
-
- if (pll_type == pll_rk3066)
- pll_mux->flags |= CLK_MUX_HIWORD_MASK;
-
mux_clk = clk_register(NULL, &pll_mux->hw);
if (IS_ERR(mux_clk))
goto err_mux;
--
2.1.1
next prev parent reply other threads:[~2014-11-20 19:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-20 19:38 [PATCH v2 0/4] clk: rockchip: allow adjusting pll rates on init Heiko Stuebner
2014-11-20 19:38 ` [PATCH v2 1/4] clk: rockchip: add ability to specify pll-specific flags Heiko Stuebner
2014-11-20 19:38 ` Heiko Stuebner [this message]
2014-11-20 19:38 ` [PATCH v2 3/4] clk: rockchip: add optional sync to pll rate parameters Heiko Stuebner
2014-11-20 19:38 ` [PATCH v2 4/4] clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls Heiko Stuebner
2014-11-21 2:56 ` [PATCH v2 0/4] clk: rockchip: allow adjusting pll rates on init Kever Yang
2014-11-25 6:11 ` Mike Turquette
2014-11-25 11:28 ` Heiko Stübner
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