[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Krzysztof Kozlowski]

Audio subsystem clocks are located in separate block. On Exynos 5420 if
clock for this block (from main clock domain) 'mau_epll' is gated then
any read or write to audss registers will block.

This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
after introducing runtime PM to pl330 DMA driver. After that commit the
'mau_epll' was gated, because the "amba" clock was disabled and there
were no more users of mau_epll.

The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because
   samsung_pinmux_setup() tried to access memory from audss block which was
   gated.

Add a workaround for this by enabling the 'mau_epll' clock in probe.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index acce708ace18..0916a81fa932 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock);
 static struct clk **clk_table;
 static void __iomem *reg_base;
 static struct clk_onecell_data clk_data;
+/*
+ * On Exynos5420 this will be a clock which has to be enabled before any
+ * access to audss registers. Typically a child of EPLL.
+ *
+ * On other platforms this will be -ENODEV.
+ */
+static struct clk *epll;
 
 #define ASS_CLK_SRC 0x0
 #define ASS_CLK_DIV 0x4
@@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failed to map audss registers\n");
 		return PTR_ERR(reg_base);
 	}
+	/* EPLL don't have to be enabled for boards other than Exynos5420 */
+	epll = ERR_PTR(-ENODEV);
 
 	clk_table = devm_kzalloc(&pdev->dev,
 				sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
@@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
 	pll_in = devm_clk_get(&pdev->dev, "pll_in");
 	if (!IS_ERR(pll_ref))
 		mout_audss_p[0] = __clk_get_name(pll_ref);
-	if (!IS_ERR(pll_in))
+	if (!IS_ERR(pll_in)) {
 		mout_audss_p[1] = __clk_get_name(pll_in);
+
+		if (variant == TYPE_EXYNOS5420) {
+			epll = pll_in;
+
+			ret = clk_prepare_enable(epll);
+			if (ret) {
+				dev_err(&pdev->dev,
+						"failed to prepare the epll clock\n");
+				return ret;
+			}
+		}
+	}
 	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
 				mout_audss_p, ARRAY_SIZE(mout_audss_p),
 				CLK_SET_RATE_NO_REPARENT,
@@ -203,6 +224,9 @@ unregister:
 			clk_unregister(clk_table[i]);
 	}
 
+	if (!IS_ERR(epll))
+		clk_disable_unprepare(epll);
+
 	return ret;
 }
 
@@ -217,6 +241,9 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
 			clk_unregister(clk_table[i]);
 	}
 
+	if (!IS_ERR(epll))
+		clk_disable_unprepare(epll);
+
 	return 0;
 }
 
-- 
1.9.1

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Krzysztof Kozlowski]

On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
> Audio subsystem clocks are located in separate block. On Exynos 5420 if
> clock for this block (from main clock domain) 'mau_epll' is gated then
> any read or write to audss registers will block.
> 
> This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
> after introducing runtime PM to pl330 DMA driver. After that commit the
> 'mau_epll' was gated, because the "amba" clock was disabled and there
> were no more users of mau_epll.
> 
> The system hang on one of steps:
> 1. Disabling unused clocks from audss block.
> 2. During audss GPIO setup (just before probing i2s0 because
>    samsung_pinmux_setup() tried to access memory from audss block which was
>    gated.
> 
> Add a workaround for this by enabling the 'mau_epll' clock in probe.
> 
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
>  1 file changed, 28 insertions(+), 1 deletion(-)

Sorry for pinging so quick but merge window is open and it looks like
booting Exynos542x boards will be broken (because pl330 will no longer
hold adma clock enabled so whole audss domain will be gated).

This is a non-intrusive workaround for that issue, as wanted by
Sylwester:
https://lkml.org/lkml/2014/12/5/223

Any comments on this?

Best regards,
Krzysztof


> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
> index acce708ace18..0916a81fa932 100644
> --- a/drivers/clk/samsung/clk-exynos-audss.c
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock);
>  static struct clk **clk_table;
>  static void __iomem *reg_base;
>  static struct clk_onecell_data clk_data;
> +/*
> + * On Exynos5420 this will be a clock which has to be enabled before any
> + * access to audss registers. Typically a child of EPLL.
> + *
> + * On other platforms this will be -ENODEV.
> + */
> +static struct clk *epll;
>  
>  #define ASS_CLK_SRC 0x0
>  #define ASS_CLK_DIV 0x4
> @@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
>  		dev_err(&pdev->dev, "failed to map audss registers\n");
>  		return PTR_ERR(reg_base);
>  	}
> +	/* EPLL don't have to be enabled for boards other than Exynos5420 */
> +	epll = ERR_PTR(-ENODEV);
>  
>  	clk_table = devm_kzalloc(&pdev->dev,
>  				sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
> @@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
>  	pll_in = devm_clk_get(&pdev->dev, "pll_in");
>  	if (!IS_ERR(pll_ref))
>  		mout_audss_p[0] = __clk_get_name(pll_ref);
> -	if (!IS_ERR(pll_in))
> +	if (!IS_ERR(pll_in)) {
>  		mout_audss_p[1] = __clk_get_name(pll_in);
> +
> +		if (variant == TYPE_EXYNOS5420) {
> +			epll = pll_in;
> +
> +			ret = clk_prepare_enable(epll);
> +			if (ret) {
> +				dev_err(&pdev->dev,
> +						"failed to prepare the epll clock\n");
> +				return ret;
> +			}
> +		}
> +	}
>  	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
>  				mout_audss_p, ARRAY_SIZE(mout_audss_p),
>  				CLK_SET_RATE_NO_REPARENT,
> @@ -203,6 +224,9 @@ unregister:
>  			clk_unregister(clk_table[i]);
>  	}
>  
> +	if (!IS_ERR(epll))
> +		clk_disable_unprepare(epll);
> +
>  	return ret;
>  }
>  
> @@ -217,6 +241,9 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
>  			clk_unregister(clk_table[i]);
>  	}
>  
> +	if (!IS_ERR(epll))
> +		clk_disable_unprepare(epll);
> +
>  	return 0;
>  }
>  

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Sylwester Nawrocki]

On 09/12/14 13:59, Krzysztof Kozlowski wrote:
> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
>> > clock for this block (from main clock domain) 'mau_epll' is gated then
>> > any read or write to audss registers will block.
>> > 
>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
>> > after introducing runtime PM to pl330 DMA driver. After that commit the
>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
>> > were no more users of mau_epll.
>> > 
>> > The system hang on one of steps:
>> > 1. Disabling unused clocks from audss block.
>> > 2. During audss GPIO setup (just before probing i2s0 because
>> >    samsung_pinmux_setup() tried to access memory from audss block which was
>> >    gated.
>> > 
>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
>> > 
>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>> > ---
>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
>> >  1 file changed, 28 insertions(+), 1 deletion(-)
>
> Sorry for pinging so quick but merge window is open and it looks like
> booting Exynos542x boards will be broken (because pl330 will no longer
> hold adma clock enabled so whole audss domain will be gated).
> 
> This is a non-intrusive workaround for that issue, as wanted by
> Sylwester:
> https://lkml.org/lkml/2014/12/5/223
> 
> Any comments on this?

The patch looks OK to me, it would be good though if someone else
has confirmed it fixes the bug. I don't have any clock patches queued
at the moment. Perhaps you could apply it directly, Mike ?

>From my side:

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

-- 
Thanks,
Sylwester

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Javier Martinez Canillas]

Hello,

On 12/09/2014 02:18 PM, Sylwester Nawrocki wrote:
>> 
>> This is a non-intrusive workaround for that issue, as wanted by
>> Sylwester:
>> https://lkml.org/lkml/2014/12/5/223
>> 
>> Any comments on this?
> 
> The patch looks OK to me, it would be good though if someone else
> has confirmed it fixes the bug. I don't have any clock patches queued
> at the moment. Perhaps you could apply it directly, Mike ?
> 

This patch fixes the boot failure bug on my Exynos5420 Peach Pit
Chromebook and I've audio working as well.

> From my side:
> 
> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> 

Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

Best regards,
Javier

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Kevin Hilman]

Sylwester Nawrocki <s.nawrocki@samsung.com> writes:

> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
>>> > any read or write to audss registers will block.
>>> > 
>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
>>> > were no more users of mau_epll.
>>> > 
>>> > The system hang on one of steps:
>>> > 1. Disabling unused clocks from audss block.
>>> > 2. During audss GPIO setup (just before probing i2s0 because
>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
>>> >    gated.
>>> > 
>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
>>> > 
>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>> > ---
>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
>>
>> Sorry for pinging so quick but merge window is open and it looks like
>> booting Exynos542x boards will be broken (because pl330 will no longer
>> hold adma clock enabled so whole audss domain will be gated).
>> 
>> This is a non-intrusive workaround for that issue, as wanted by
>> Sylwester:
>> https://lkml.org/lkml/2014/12/5/223
>> 
>> Any comments on this?
>
> The patch looks OK to me, it would be good though if someone else
> has confirmed it fixes the bug. I don't have any clock patches queued
> at the moment. Perhaps you could apply it directly, Mike ?

I confirm it fixes the boot hang in linux-next (next-20141210) on my
exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
exynos_defconfig and multi_v7_defconfig.

Tested-by: Kevin Hilman <khilman@linaro.org>

Kevin

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Kevin Hilman]

Kevin Hilman <khilman@kernel.org> writes:

> Sylwester Nawrocki <s.nawrocki@samsung.com> writes:
>
>> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
>>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
>>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
>>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
>>>> > any read or write to audss registers will block.
>>>> > 
>>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
>>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
>>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
>>>> > were no more users of mau_epll.
>>>> > 
>>>> > The system hang on one of steps:
>>>> > 1. Disabling unused clocks from audss block.
>>>> > 2. During audss GPIO setup (just before probing i2s0 because
>>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
>>>> >    gated.
>>>> > 
>>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
>>>> > 
>>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>>> > ---
>>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
>>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
>>>
>>> Sorry for pinging so quick but merge window is open and it looks like
>>> booting Exynos542x boards will be broken (because pl330 will no longer
>>> hold adma clock enabled so whole audss domain will be gated).
>>> 
>>> This is a non-intrusive workaround for that issue, as wanted by
>>> Sylwester:
>>> https://lkml.org/lkml/2014/12/5/223
>>> 
>>> Any comments on this?
>>
>> The patch looks OK to me, it would be good though if someone else
>> has confirmed it fixes the bug. I don't have any clock patches queued
>> at the moment. Perhaps you could apply it directly, Mike ?
>
> I confirm it fixes the boot hang in linux-next (next-20141210) on my
> exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
> exynos_defconfig and multi_v7_defconfig.
>
> Tested-by: Kevin Hilman <khilman@linaro.org>

What's the status of this patch?  linux-next is still broken for several
Exynos5 platforms without this fix.

Kevin

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Krzysztof Kozlowski]

On pon, 2014-12-15 at 14:26 -0800, Kevin Hilman wrote:
> Kevin Hilman <khilman@kernel.org> writes:
> 
> > Sylwester Nawrocki <s.nawrocki@samsung.com> writes:
> >
> >> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
> >>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
> >>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
> >>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
> >>>> > any read or write to audss registers will block.
> >>>> > 
> >>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
> >>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
> >>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
> >>>> > were no more users of mau_epll.
> >>>> > 
> >>>> > The system hang on one of steps:
> >>>> > 1. Disabling unused clocks from audss block.
> >>>> > 2. During audss GPIO setup (just before probing i2s0 because
> >>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
> >>>> >    gated.
> >>>> > 
> >>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
> >>>> > 
> >>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> >>>> > ---
> >>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
> >>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
> >>>
> >>> Sorry for pinging so quick but merge window is open and it looks like
> >>> booting Exynos542x boards will be broken (because pl330 will no longer
> >>> hold adma clock enabled so whole audss domain will be gated).
> >>> 
> >>> This is a non-intrusive workaround for that issue, as wanted by
> >>> Sylwester:
> >>> https://lkml.org/lkml/2014/12/5/223
> >>> 
> >>> Any comments on this?
> >>
> >> The patch looks OK to me, it would be good though if someone else
> >> has confirmed it fixes the bug. I don't have any clock patches queued
> >> at the moment. Perhaps you could apply it directly, Mike ?
> >
> > I confirm it fixes the boot hang in linux-next (next-20141210) on my
> > exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
> > exynos_defconfig and multi_v7_defconfig.
> >
> > Tested-by: Kevin Hilman <khilman@linaro.org>
> 
> What's the status of this patch?  linux-next is still broken for several
> Exynos5 platforms without this fix.

I believe not only next is broken but also current mainline because
runtime PM for pl330 was merged yesterday...

The patch received two tested-bys (Kevin's and Javier's) and Sylwester's
ack.

Mike, could you pick the patch and send it to Linus after rc1?

Best regards,
Krzysztof

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Mike Turquette]

Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
> On pon, 2014-12-15 at 14:26 -0800, Kevin Hilman wrote:
> > Kevin Hilman <khilman@kernel.org> writes:
> > 
> > > Sylwester Nawrocki <s.nawrocki@samsung.com> writes:
> > >
> > >> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
> > >>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
> > >>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
> > >>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
> > >>>> > any read or write to audss registers will block.
> > >>>> > 
> > >>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
> > >>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
> > >>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
> > >>>> > were no more users of mau_epll.
> > >>>> > 
> > >>>> > The system hang on one of steps:
> > >>>> > 1. Disabling unused clocks from audss block.
> > >>>> > 2. During audss GPIO setup (just before probing i2s0 because
> > >>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
> > >>>> >    gated.
> > >>>> > 
> > >>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
> > >>>> > 
> > >>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> > >>>> > ---
> > >>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
> > >>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
> > >>>
> > >>> Sorry for pinging so quick but merge window is open and it looks like
> > >>> booting Exynos542x boards will be broken (because pl330 will no longer
> > >>> hold adma clock enabled so whole audss domain will be gated).
> > >>> 
> > >>> This is a non-intrusive workaround for that issue, as wanted by
> > >>> Sylwester:
> > >>> https://lkml.org/lkml/2014/12/5/223
> > >>> 
> > >>> Any comments on this?
> > >>
> > >> The patch looks OK to me, it would be good though if someone else
> > >> has confirmed it fixes the bug. I don't have any clock patches queued
> > >> at the moment. Perhaps you could apply it directly, Mike ?
> > >
> > > I confirm it fixes the boot hang in linux-next (next-20141210) on my
> > > exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
> > > exynos_defconfig and multi_v7_defconfig.
> > >
> > > Tested-by: Kevin Hilman <khilman@linaro.org>
> > 
> > What's the status of this patch?  linux-next is still broken for several
> > Exynos5 platforms without this fix.
> 
> I believe not only next is broken but also current mainline because
> runtime PM for pl330 was merged yesterday...
> 
> The patch received two tested-bys (Kevin's and Javier's) and Sylwester's
> ack.
> 
> Mike, could you pick the patch and send it to Linus after rc1?

Will do.

Regards,
Mike

> 
> Best regards,
> Krzysztof
> 

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Mike Turquette]

Quoting Mike Turquette (2014-12-17 07:23:22)
> Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
> > On pon, 2014-12-15 at 14:26 -0800, Kevin Hilman wrote:
> > > Kevin Hilman <khilman@kernel.org> writes:
> > > 
> > > > Sylwester Nawrocki <s.nawrocki@samsung.com> writes:
> > > >
> > > >> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
> > > >>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
> > > >>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
> > > >>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
> > > >>>> > any read or write to audss registers will block.
> > > >>>> > 
> > > >>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
> > > >>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
> > > >>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
> > > >>>> > were no more users of mau_epll.
> > > >>>> > 
> > > >>>> > The system hang on one of steps:
> > > >>>> > 1. Disabling unused clocks from audss block.
> > > >>>> > 2. During audss GPIO setup (just before probing i2s0 because
> > > >>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
> > > >>>> >    gated.
> > > >>>> > 
> > > >>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
> > > >>>> > 
> > > >>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> > > >>>> > ---
> > > >>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
> > > >>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
> > > >>>
> > > >>> Sorry for pinging so quick but merge window is open and it looks like
> > > >>> booting Exynos542x boards will be broken (because pl330 will no longer
> > > >>> hold adma clock enabled so whole audss domain will be gated).
> > > >>> 
> > > >>> This is a non-intrusive workaround for that issue, as wanted by
> > > >>> Sylwester:
> > > >>> https://lkml.org/lkml/2014/12/5/223
> > > >>> 
> > > >>> Any comments on this?
> > > >>
> > > >> The patch looks OK to me, it would be good though if someone else
> > > >> has confirmed it fixes the bug. I don't have any clock patches queued
> > > >> at the moment. Perhaps you could apply it directly, Mike ?
> > > >
> > > > I confirm it fixes the boot hang in linux-next (next-20141210) on my
> > > > exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
> > > > exynos_defconfig and multi_v7_defconfig.
> > > >
> > > > Tested-by: Kevin Hilman <khilman@linaro.org>
> > > 
> > > What's the status of this patch?  linux-next is still broken for several
> > > Exynos5 platforms without this fix.
> > 
> > I believe not only next is broken but also current mainline because
> > runtime PM for pl330 was merged yesterday...
> > 
> > The patch received two tested-bys (Kevin's and Javier's) and Sylwester's
> > ack.
> > 
> > Mike, could you pick the patch and send it to Linus after rc1?
> 
> Will do.

To be clear, I pulled this into clk-next towards -rc1, so it won't need
to go through as an -rc fix.

Regards,
Mike

> 
> Regards,
> Mike
> 
> > 
> > Best regards,
> > Krzysztof
> > 

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Kevin Hilman]

On Wed, Dec 17, 2014 at 10:58 PM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Mike Turquette (2014-12-17 07:23:22)
>> Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
>> > On pon, 2014-12-15 at 14:26 -0800, Kevin Hilman wrote:
>> > > Kevin Hilman <khilman@kernel.org> writes:
>> > >
>> > > > Sylwester Nawrocki <s.nawrocki@samsung.com> writes:
>> > > >
>> > > >> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
>> > > >>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
>> > > >>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
>> > > >>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
>> > > >>>> > any read or write to audss registers will block.
>> > > >>>> >
>> > > >>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
>> > > >>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
>> > > >>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
>> > > >>>> > were no more users of mau_epll.
>> > > >>>> >
>> > > >>>> > The system hang on one of steps:
>> > > >>>> > 1. Disabling unused clocks from audss block.
>> > > >>>> > 2. During audss GPIO setup (just before probing i2s0 because
>> > > >>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
>> > > >>>> >    gated.
>> > > >>>> >
>> > > >>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
>> > > >>>> >
>> > > >>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>> > > >>>> > ---
>> > > >>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
>> > > >>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
>> > > >>>
>> > > >>> Sorry for pinging so quick but merge window is open and it looks like
>> > > >>> booting Exynos542x boards will be broken (because pl330 will no longer
>> > > >>> hold adma clock enabled so whole audss domain will be gated).
>> > > >>>
>> > > >>> This is a non-intrusive workaround for that issue, as wanted by
>> > > >>> Sylwester:
>> > > >>> https://lkml.org/lkml/2014/12/5/223
>> > > >>>
>> > > >>> Any comments on this?
>> > > >>
>> > > >> The patch looks OK to me, it would be good though if someone else
>> > > >> has confirmed it fixes the bug. I don't have any clock patches queued
>> > > >> at the moment. Perhaps you could apply it directly, Mike ?
>> > > >
>> > > > I confirm it fixes the boot hang in linux-next (next-20141210) on my
>> > > > exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
>> > > > exynos_defconfig and multi_v7_defconfig.
>> > > >
>> > > > Tested-by: Kevin Hilman <khilman@linaro.org>
>> > >
>> > > What's the status of this patch?  linux-next is still broken for several
>> > > Exynos5 platforms without this fix.
>> >
>> > I believe not only next is broken but also current mainline because
>> > runtime PM for pl330 was merged yesterday...
>> >
>> > The patch received two tested-bys (Kevin's and Javier's) and Sylwester's
>> > ack.
>> >
>> > Mike, could you pick the patch and send it to Linus after rc1?
>>
>> Will do.
>
> To be clear, I pulled this into clk-next towards -rc1, so it won't need
> to go through as an -rc fix.

This hit today's linux-next, and exynos5 platforms are happily booting
again.  Thanks!

Kevin

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Mike Turquette]

Quoting Kevin Hilman (2014-12-18 14:10:34)
> On Wed, Dec 17, 2014 at 10:58 PM, Mike Turquette <mturquette@linaro.org> wrote:
> > Quoting Mike Turquette (2014-12-17 07:23:22)
> >> Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
> >> > On pon, 2014-12-15 at 14:26 -0800, Kevin Hilman wrote:
> >> > > Kevin Hilman <khilman@kernel.org> writes:
> >> > >
> >> > > > Sylwester Nawrocki <s.nawrocki@samsung.com> writes:
> >> > > >
> >> > > >> On 09/12/14 13:59, Krzysztof Kozlowski wrote:
> >> > > >>> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote:
> >> > > >>>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if
> >> > > >>>> > clock for this block (from main clock domain) 'mau_epll' is gated then
> >> > > >>>> > any read or write to audss registers will block.
> >> > > >>>> >
> >> > > >>>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
> >> > > >>>> > after introducing runtime PM to pl330 DMA driver. After that commit the
> >> > > >>>> > 'mau_epll' was gated, because the "amba" clock was disabled and there
> >> > > >>>> > were no more users of mau_epll.
> >> > > >>>> >
> >> > > >>>> > The system hang on one of steps:
> >> > > >>>> > 1. Disabling unused clocks from audss block.
> >> > > >>>> > 2. During audss GPIO setup (just before probing i2s0 because
> >> > > >>>> >    samsung_pinmux_setup() tried to access memory from audss block which was
> >> > > >>>> >    gated.
> >> > > >>>> >
> >> > > >>>> > Add a workaround for this by enabling the 'mau_epll' clock in probe.
> >> > > >>>> >
> >> > > >>>> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> >> > > >>>> > ---
> >> > > >>>> >  drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
> >> > > >>>> >  1 file changed, 28 insertions(+), 1 deletion(-)
> >> > > >>>
> >> > > >>> Sorry for pinging so quick but merge window is open and it looks like
> >> > > >>> booting Exynos542x boards will be broken (because pl330 will no longer
> >> > > >>> hold adma clock enabled so whole audss domain will be gated).
> >> > > >>>
> >> > > >>> This is a non-intrusive workaround for that issue, as wanted by
> >> > > >>> Sylwester:
> >> > > >>> https://lkml.org/lkml/2014/12/5/223
> >> > > >>>
> >> > > >>> Any comments on this?
> >> > > >>
> >> > > >> The patch looks OK to me, it would be good though if someone else
> >> > > >> has confirmed it fixes the bug. I don't have any clock patches queued
> >> > > >> at the moment. Perhaps you could apply it directly, Mike ?
> >> > > >
> >> > > > I confirm it fixes the boot hang in linux-next (next-20141210) on my
> >> > > > exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
> >> > > > exynos_defconfig and multi_v7_defconfig.
> >> > > >
> >> > > > Tested-by: Kevin Hilman <khilman@linaro.org>
> >> > >
> >> > > What's the status of this patch?  linux-next is still broken for several
> >> > > Exynos5 platforms without this fix.
> >> >
> >> > I believe not only next is broken but also current mainline because
> >> > runtime PM for pl330 was merged yesterday...
> >> >
> >> > The patch received two tested-bys (Kevin's and Javier's) and Sylwester's
> >> > ack.
> >> >
> >> > Mike, could you pick the patch and send it to Linus after rc1?
> >>
> >> Will do.
> >
> > To be clear, I pulled this into clk-next towards -rc1, so it won't need
> > to go through as an -rc fix.
> 
> This hit today's linux-next, and exynos5 platforms are happily booting
> again.  Thanks!

Thanks for testing it Kevin.

Regards,
Mike

> 
> Kevin

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Paolo Pisati]

On Wed, Dec 10, 2014 at 09:35:31AM -0800, Kevin Hilman wrote:
> 
> I confirm it fixes the boot hang in linux-next (next-20141210) on my
> exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
> exynos_defconfig and multi_v7_defconfig.
> 
> Tested-by: Kevin Hilman <khilman@linaro.org>

does audio work on your peach pi? because kernel boots fine, but i can't get any
audio out of it

-- 
bye,
p.

[PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

[Javier Martinez Canillas]

Hello Paolo,

On 12/24/2014 05:36 PM, Paolo Pisati wrote:
> On Wed, Dec 10, 2014 at 09:35:31AM -0800, Kevin Hilman wrote:
>> 
>> I confirm it fixes the boot hang in linux-next (next-20141210) on my
>> exynos5800-peach-pi and exynos5420-arndale-octa.  Tested both
>> exynos_defconfig and multi_v7_defconfig.
>> 
>> Tested-by: Kevin Hilman <khilman@linaro.org>
> 
> does audio work on your peach pi? because kernel boots fine, but i can't get any
> audio out of it
> 

Audio is not working for me as well. I said before that audio was working
because I tested with the headphone audio jack but I forgot that I had
re-introduced the clk_ignore_unused parameter to my kernel command line
to test the mmc/sdio wifi. Without clk_ignore_unused, I have no audio.

I see that the downstream daisy_max98095 ASoC driver in the ChromeOS tree
grabs some clocks that the mainline sound/soc/samsung/snow.c driver so it
it seems that at least that is missing and may explain why it is working
with clk_ignore_unused.

Best regards,
Javier