* [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks
@ 2014-12-16 19:30 Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 2/2] ARM: dts: imx6sx-sdb: Add QSPI support Fabio Estevam
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Fabio Estevam @ 2014-12-16 19:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@freescale.com>
The default qspi2_clk_sel field of register CCM_CS2CDR contains '110' which is
marked as 'reserved', so we can't rely on the default value.
Provide a proper parent for QSPI clocks to avoid a kernel oops:
[ 1.037920] Division by zero in kernel.
[ 1.041807] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.18.0-rc7-next-20141204-00002-g5aa23e1 #2143
[ 1.050967] Hardware name: Freescale i.MX6 SoloX (Device Tree)
[ 1.056853] Backtrace:
[ 1.059360] [<80011ea0>] (dump_backtrace) from [<8001203c>] (show_stack+0x18/0x1c)
[ 1.066982] r6:00000000 r5:00000000 r4:00000000 r3:00000000
[ 1.072754] [<80012024>] (show_stack) from [<806b7100>] (dump_stack+0x88/0xa4)
[ 1.080038] [<806b7078>] (dump_stack) from [<80011d20>] (__div0+0x18/0x20)
[ 1.086958] r5:be018500 r4:be017c00
[ 1.090600] [<80011d08>] (__div0) from [<802aa418>] (Ldiv0+0x8/0x10)
[ 1.097012] [<80504fbc>] (clk_divider_set_rate) from [<80503ddc>] (clk_change_rate+0x14c/0x17c)
[ 1.105759] r7:00000000 r6:00000000 r5:be018500 r4:00000000
[ 1.111516] [<80503c90>] (clk_change_rate) from [<80503ea0>] (clk_set_rate+0x94/0x98)
[ 1.119391] r8:be7e0368 r7:00000000 r6:be11a000 r5:be018500 r4:00000000 r3:00000000
[ 1.127290] [<80503e0c>] (clk_set_rate) from [<80410558>] (fsl_qspi_probe+0x23c/0x75c)
[ 1.135260] r5:be11a010 r4:be350010
[ 1.138900] [<8041031c>] (fsl_qspi_probe) from [<80385a18>] (platform_drv_probe+0x50/0xac)
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Explain why we can't rely on the defauly qspi2 clock parent
arch/arm/mach-imx/clk-imx6sx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 17354a1..5a3e5a1 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+ clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
+ clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
+
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2 2/2] ARM: dts: imx6sx-sdb: Add QSPI support
2014-12-16 19:30 [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Fabio Estevam
@ 2014-12-16 19:30 ` Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 3/3] ARM: imx_v6_v7_defconfig: Select SPI_FSL_QUADSPI by default Fabio Estevam
2015-01-05 13:26 ` [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Shawn Guo
2 siblings, 0 replies; 4+ messages in thread
From: Fabio Estevam @ 2014-12-16 19:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@freescale.com>
imx6sx-sdb has two s25fl128s quad spi flash. Add support for them.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None
arch/arm/boot/dts/imx6sx-sdb.dts | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 1e6e5cc..cdffe84 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -340,6 +340,28 @@
status = "okay";
};
+&qspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi2>;
+ status = "okay";
+
+ flash0: s25fl128s at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl128s";
+ spi-max-frequency = <66000000>;
+ };
+
+ flash1: s25fl128s at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl128s";
+ spi-max-frequency = <66000000>;
+ };
+};
+
&ssi2 {
status = "okay";
};
@@ -524,6 +546,23 @@
>;
};
+ pinctrl_qspi2: qspi2grp {
+ fsl,pins = <
+ MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
+ MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
+ MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
+ MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
+ MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
+ MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
+ MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
+ MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
+ MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
+ MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
+ MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
+ MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
+ >;
+ };
+
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2 3/3] ARM: imx_v6_v7_defconfig: Select SPI_FSL_QUADSPI by default
2014-12-16 19:30 [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 2/2] ARM: dts: imx6sx-sdb: Add QSPI support Fabio Estevam
@ 2014-12-16 19:30 ` Fabio Estevam
2015-01-05 13:26 ` [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Shawn Guo
2 siblings, 0 replies; 4+ messages in thread
From: Fabio Estevam @ 2014-12-16 19:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@freescale.com>
SPI_FSL_QUADSPI can be used by Vybrid and mx6sx, so select it by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6790f1b..c405a04 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -97,6 +97,7 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_FSL_QUADSPI=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks
2014-12-16 19:30 [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 2/2] ARM: dts: imx6sx-sdb: Add QSPI support Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 3/3] ARM: imx_v6_v7_defconfig: Select SPI_FSL_QUADSPI by default Fabio Estevam
@ 2015-01-05 13:26 ` Shawn Guo
2 siblings, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2015-01-05 13:26 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Dec 16, 2014 at 05:30:28PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> The default qspi2_clk_sel field of register CCM_CS2CDR contains '110' which is
> marked as 'reserved', so we can't rely on the default value.
>
> Provide a proper parent for QSPI clocks to avoid a kernel oops:
>
> [ 1.037920] Division by zero in kernel.
> [ 1.041807] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.18.0-rc7-next-20141204-00002-g5aa23e1 #2143
> [ 1.050967] Hardware name: Freescale i.MX6 SoloX (Device Tree)
> [ 1.056853] Backtrace:
> [ 1.059360] [<80011ea0>] (dump_backtrace) from [<8001203c>] (show_stack+0x18/0x1c)
> [ 1.066982] r6:00000000 r5:00000000 r4:00000000 r3:00000000
> [ 1.072754] [<80012024>] (show_stack) from [<806b7100>] (dump_stack+0x88/0xa4)
> [ 1.080038] [<806b7078>] (dump_stack) from [<80011d20>] (__div0+0x18/0x20)
> [ 1.086958] r5:be018500 r4:be017c00
> [ 1.090600] [<80011d08>] (__div0) from [<802aa418>] (Ldiv0+0x8/0x10)
> [ 1.097012] [<80504fbc>] (clk_divider_set_rate) from [<80503ddc>] (clk_change_rate+0x14c/0x17c)
> [ 1.105759] r7:00000000 r6:00000000 r5:be018500 r4:00000000
> [ 1.111516] [<80503c90>] (clk_change_rate) from [<80503ea0>] (clk_set_rate+0x94/0x98)
> [ 1.119391] r8:be7e0368 r7:00000000 r6:be11a000 r5:be018500 r4:00000000 r3:00000000
> [ 1.127290] [<80503e0c>] (clk_set_rate) from [<80410558>] (fsl_qspi_probe+0x23c/0x75c)
> [ 1.135260] r5:be11a010 r4:be350010
> [ 1.138900] [<8041031c>] (fsl_qspi_probe) from [<80385a18>] (platform_drv_probe+0x50/0xac)
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Applied all 3, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-01-05 13:26 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-12-16 19:30 [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 2/2] ARM: dts: imx6sx-sdb: Add QSPI support Fabio Estevam
2014-12-16 19:30 ` [PATCH v2 3/3] ARM: imx_v6_v7_defconfig: Select SPI_FSL_QUADSPI by default Fabio Estevam
2015-01-05 13:26 ` [PATCH v2 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks Shawn Guo
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).