[PATCH v2 0/3] ARM: dts: berlin: add PMU and twd's cpu mask and fix GPIO locations

[PATCH v2 0/3] ARM: dts: berlin: add PMU and twd's cpu mask and fix GPIO locations

[Jisheng Zhang]

These patches try to improve dts for berlin. One of them enables PMU support
to BG2Q and BG2CD SoCs. One of them adds the missing PPI cpu mask to twd timer
interrupts. The last one corrects the SM GPIOs' location for BG2Q SoC.

Changes since v1:
 - Adds some text to the log of the second commit
 - Adds the patch to fix SM GPIO locations

Jisheng Zhang (3):
  ARM: dts: berlin: add pmu node for BG2Q and BG2CD
  ARM: dts: berlin: add PPI cpu mask to twd timer interrupts
  ARM: dts: berlin: correct BG2Q's SM GPIO location.

 arch/arm/boot/dts/berlin2.dtsi   |  2 +-
 arch/arm/boot/dts/berlin2cd.dtsi |  7 +++-
 arch/arm/boot/dts/berlin2q.dtsi  | 70 ++++++++++++++++++++++------------------
 3 files changed, 46 insertions(+), 33 deletions(-)

-- 
2.1.4

[PATCH v2 1/3] ARM: dts: berlin: add pmu node for BG2Q and BG2CD

[Jisheng Zhang]

This patch adds the pmu node, enabling the PMU unit on Marvell BG2Q and
BG2CD SoCs.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 5 +++++
 arch/arm/boot/dts/berlin2q.dtsi  | 8 ++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 230df3b..a318bc3 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,11 @@
 
 		ranges = <0 0xf7000000 0x1000000>;
 
+		pmu {
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		sdhci0: sdhci at ab0000 {
 			compatible = "mrvl,pxav3-mmc";
 			reg = <0xab0000 0x200>;
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 35253c9..933dcbb 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -63,6 +63,14 @@
 		ranges = <0 0xf7000000 0x1000000>;
 		interrupt-parent = <&gic>;
 
+		pmu {
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		sdhci0: sdhci at ab0000 {
 			compatible = "mrvl,pxav3-mmc";
 			reg = <0xab0000 0x200>;
-- 
2.1.4

[PATCH v2 1/3] ARM: dts: berlin: add pmu node for BG2Q and BG2CD

[Sebastian Hesselbarth]

On 26.12.2014 09:57, Jisheng Zhang wrote:
> This patch adds the pmu node, enabling the PMU unit on Marvell BG2Q and
> BG2CD SoCs.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>

Applied to berlin/dt.

Thanks!

> ---
>   arch/arm/boot/dts/berlin2cd.dtsi | 5 +++++
>   arch/arm/boot/dts/berlin2q.dtsi  | 8 ++++++++
>   2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
> index 230df3b..a318bc3 100644
> --- a/arch/arm/boot/dts/berlin2cd.dtsi
> +++ b/arch/arm/boot/dts/berlin2cd.dtsi
> @@ -45,6 +45,11 @@
>
>   		ranges = <0 0xf7000000 0x1000000>;
>
> +		pmu {
> +			compatible = "arm,cortex-a9-pmu";
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>   		sdhci0: sdhci at ab0000 {
>   			compatible = "mrvl,pxav3-mmc";
>   			reg = <0xab0000 0x200>;
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 35253c9..933dcbb 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -63,6 +63,14 @@
>   		ranges = <0 0xf7000000 0x1000000>;
>   		interrupt-parent = <&gic>;
>
> +		pmu {
> +			compatible = "arm,cortex-a9-pmu";
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>   		sdhci0: sdhci at ab0000 {
>   			compatible = "mrvl,pxav3-mmc";
>   			reg = <0xab0000 0x200>;
>

[PATCH v2 2/3] ARM: dts: berlin: add PPI cpu mask to twd timer interrupts

[Jisheng Zhang]

According to the gic binding document, "bits[15:8] PPI interrupt cpu
mask.  Each bit corresponds to each of the 8 possible cpus attached to
the GIC.  A bit set to '1' indicated the interrupt is wired to that
CPU." This patch wants to add the PPI cpu mask for completeness.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 arch/arm/boot/dts/berlin2.dtsi   | 2 +-
 arch/arm/boot/dts/berlin2cd.dtsi | 2 +-
 arch/arm/boot/dts/berlin2q.dtsi  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 015a06c..63d00a6 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -104,7 +104,7 @@
 		local-timer at ad0600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
-			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&chip CLKID_TWD>;
 		};
 
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index a318bc3..81b670a 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -76,7 +76,7 @@
 		local-timer at ad0600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
-			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&chip CLKID_TWD>;
 		};
 
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 933dcbb..41a683f 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -112,7 +112,7 @@
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
 			clocks = <&chip CLKID_TWD>;
-			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
 		gic: interrupt-controller at ad1000 {
-- 
2.1.4

[PATCH v2 2/3] ARM: dts: berlin: add PPI cpu mask to twd timer interrupts

[Sebastian Hesselbarth]

On 26.12.2014 09:58, Jisheng Zhang wrote:
> According to the gic binding document, "bits[15:8] PPI interrupt cpu
> mask.  Each bit corresponds to each of the 8 possible cpus attached to
> the GIC.  A bit set to '1' indicated the interrupt is wired to that
> CPU." This patch wants to add the PPI cpu mask for completeness.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>

Applied to berlin/dt.

Thanks!

> ---
>   arch/arm/boot/dts/berlin2.dtsi   | 2 +-
>   arch/arm/boot/dts/berlin2cd.dtsi | 2 +-
>   arch/arm/boot/dts/berlin2q.dtsi  | 2 +-
>   3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
> index 015a06c..63d00a6 100644
> --- a/arch/arm/boot/dts/berlin2.dtsi
> +++ b/arch/arm/boot/dts/berlin2.dtsi
> @@ -104,7 +104,7 @@
>   		local-timer at ad0600 {
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
> -			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>   			clocks = <&chip CLKID_TWD>;
>   		};
>
> diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
> index a318bc3..81b670a 100644
> --- a/arch/arm/boot/dts/berlin2cd.dtsi
> +++ b/arch/arm/boot/dts/berlin2cd.dtsi
> @@ -76,7 +76,7 @@
>   		local-timer at ad0600 {
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
> -			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
>   			clocks = <&chip CLKID_TWD>;
>   		};
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 933dcbb..41a683f 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -112,7 +112,7 @@
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
>   			clocks = <&chip CLKID_TWD>;
> -			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>   		};
>
>   		gic: interrupt-controller at ad1000 {
>

[PATCH v2 3/3] ARM: dts: berlin: correct BG2Q's SM GPIO location.

[Jisheng Zhang]

The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain.
This patch moves gpio4 and gpio5 to the correct location. This patch also
renames them as the following to match the names we internally used in
marvell:
	gpio4 -> sm_gpio1
	gpio5 -> sm_gpio0
	porte -> portf
	portf -> porte

This also matches what we did for BG2 and BG2CD's SM GPIO.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 arch/arm/boot/dts/berlin2q.dtsi | 60 ++++++++++++++++++++---------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 41a683f..f0ddbec 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -356,36 +356,6 @@
 				interrupt-parent = <&gic>;
 				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			};
-
-			gpio4: gpio at 5000 {
-				compatible = "snps,dw-apb-gpio";
-				reg = <0x5000 0x400>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				porte: gpio-port at 4 {
-					compatible = "snps,dw-apb-gpio-port";
-					gpio-controller;
-					#gpio-cells = <2>;
-					snps,nr-gpios = <32>;
-					reg = <0>;
-				};
-			};
-
-			gpio5: gpio at c000 {
-				compatible = "snps,dw-apb-gpio";
-				reg = <0xc000 0x400>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				portf: gpio-port at 5 {
-					compatible = "snps,dw-apb-gpio-port";
-					gpio-controller;
-					#gpio-cells = <2>;
-					snps,nr-gpios = <32>;
-					reg = <0>;
-				};
-			};
 		};
 
 		chip: chip-control at ea0000 {
@@ -474,6 +444,21 @@
 			ranges = <0 0xfc0000 0x10000>;
 			interrupt-parent = <&sic>;
 
+			sm_gpio1: gpio at 5000 {
+				compatible = "snps,dw-apb-gpio";
+				reg = <0x5000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				portf: gpio-port at 5 {
+					compatible = "snps,dw-apb-gpio-port";
+					gpio-controller;
+					#gpio-cells = <2>;
+					snps,nr-gpios = <32>;
+					reg = <0>;
+				};
+			};
+
 			i2c2: i2c at 7000 {
 				compatible = "snps,designware-i2c";
 				#address-cells = <1>;
@@ -524,6 +509,21 @@
 				status = "disabled";
 			};
 
+			sm_gpio0: gpio at c000 {
+				compatible = "snps,dw-apb-gpio";
+				reg = <0xc000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				porte: gpio-port at 4 {
+					compatible = "snps,dw-apb-gpio-port";
+					gpio-controller;
+					#gpio-cells = <2>;
+					snps,nr-gpios = <32>;
+					reg = <0>;
+				};
+			};
+
 			sysctrl: pin-controller at d000 {
 				compatible = "marvell,berlin2q-system-ctrl";
 				reg = <0xd000 0x100>;
-- 
2.1.4

[PATCH v2 3/3] ARM: dts: berlin: correct BG2Q's SM GPIO location.

[Sebastian Hesselbarth]

On 26.12.2014 09:58, Jisheng Zhang wrote:
> The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain.
> This patch moves gpio4 and gpio5 to the correct location. This patch also
> renames them as the following to match the names we internally used in
> marvell:
> 	gpio4 -> sm_gpio1
> 	gpio5 -> sm_gpio0
> 	porte -> portf
> 	portf -> porte
>
> This also matches what we did for BG2 and BG2CD's SM GPIO.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>

Jisheng,

please do not add unrelated patches to an existing patch set.

Anyway, applied to berlin/fixes. It will also be Cc'd to stable
from 3.16 onwards due to the broken gpio base address.

Thanks!

Sebastian

> ---
>   arch/arm/boot/dts/berlin2q.dtsi | 60 ++++++++++++++++++++---------------------
>   1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 41a683f..f0ddbec 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -356,36 +356,6 @@
>   				interrupt-parent = <&gic>;
>   				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>   			};
> -
> -			gpio4: gpio at 5000 {
> -				compatible = "snps,dw-apb-gpio";
> -				reg = <0x5000 0x400>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -
> -				porte: gpio-port at 4 {
> -					compatible = "snps,dw-apb-gpio-port";
> -					gpio-controller;
> -					#gpio-cells = <2>;
> -					snps,nr-gpios = <32>;
> -					reg = <0>;
> -				};
> -			};
> -
> -			gpio5: gpio at c000 {
> -				compatible = "snps,dw-apb-gpio";
> -				reg = <0xc000 0x400>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -
> -				portf: gpio-port at 5 {
> -					compatible = "snps,dw-apb-gpio-port";
> -					gpio-controller;
> -					#gpio-cells = <2>;
> -					snps,nr-gpios = <32>;
> -					reg = <0>;
> -				};
> -			};
>   		};
>
>   		chip: chip-control at ea0000 {
> @@ -474,6 +444,21 @@
>   			ranges = <0 0xfc0000 0x10000>;
>   			interrupt-parent = <&sic>;
>
> +			sm_gpio1: gpio at 5000 {
> +				compatible = "snps,dw-apb-gpio";
> +				reg = <0x5000 0x400>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				portf: gpio-port at 5 {
> +					compatible = "snps,dw-apb-gpio-port";
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					snps,nr-gpios = <32>;
> +					reg = <0>;
> +				};
> +			};
> +
>   			i2c2: i2c at 7000 {
>   				compatible = "snps,designware-i2c";
>   				#address-cells = <1>;
> @@ -524,6 +509,21 @@
>   				status = "disabled";
>   			};
>
> +			sm_gpio0: gpio at c000 {
> +				compatible = "snps,dw-apb-gpio";
> +				reg = <0xc000 0x400>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				porte: gpio-port at 4 {
> +					compatible = "snps,dw-apb-gpio-port";
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					snps,nr-gpios = <32>;
> +					reg = <0>;
> +				};
> +			};
> +
>   			sysctrl: pin-controller at d000 {
>   				compatible = "marvell,berlin2q-system-ctrl";
>   				reg = <0xd000 0x100>;
>