[PATCH 0/4] Add sd/emmc support for stih407 family silicon

[PATCH 0/4] Add sd/emmc support for stih407 family silicon

[Peter Griffin]

Hi,

This series adds sd/emmc support to the sdhci-st.c driver for stih407
family silicon. The changes mainly involve congiguring some extra glue
registers which configure the controller.

This series also adds support for UHS modes for eMMC. To allow
UHS HS200/SD104 modes to function correctly, due to the
tight timing constriants and data tuning requirement, support
for PVT independent delay management is also added. Two types
of delay management are supported, static delay management and
dynamic delay management (dynamic delay loop), this delay
management is only available on eMMC pads on stih410 and later
silicon.

This has been tested with stih410-b2120 on eMMC and sd, at various
clock speeds. As part of this testing a bug was also found in the
upstream flexgen clock set_rate implementation.

    max-frequency = 200Mhz
    /dev/mmcblk0p1:
     Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
    
    max-frequency = 100Mhz
    root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
    /dev/mmcblk0p1:
     Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
    
    max-frequency = 50Mhz
    root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
    /dev/mmcblk0p1:
     Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

It has also been tested on stih416-b2020 to ensure we have caused no
regressions. Finally the dt documentation has been updated to reflect
the changes in the driver code. Intrestingly it seems we are the first
upstream platform to be using some of the uhs bindings such as
sd-uhs-sdr104.

regards,

Peter.

Peter Griffin (4):
  clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate
  sdhci-st: Add support for stih407 family silicon.
  mmc: sdhci-st: Update ST SDHCI binding documentation.
  ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

 Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 +++++-
 arch/arm/boot/dts/stih407-family.dtsi              |  30 ++
 arch/arm/boot/dts/stih410-b2120.dts                |  10 +
 arch/arm/boot/dts/stihxxx-b2120.dtsi               |   8 +
 drivers/clk/st/clk-flexgen.c                       |  19 +-
 drivers/mmc/host/sdhci-st.c                        | 351 ++++++++++++++++++++-
 6 files changed, 496 insertions(+), 22 deletions(-)

-- 
1.9.1

[PATCH 1/4] clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate

[Peter Griffin]

Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.

Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.

The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.

Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.

I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/clk/st/clk-flexgen.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 2282cef..3a484b3 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -138,16 +138,27 @@ static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct flexgen *flexgen = to_flexgen(hw);
 	struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
 	struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
-	unsigned long primary_div = 0;
+	unsigned long div = 0;
 	int ret = 0;
 
 	pdiv_hw->clk = hw->clk;
 	fdiv_hw->clk = hw->clk;
 
-	primary_div = clk_best_div(parent_rate, rate);
+	div = clk_best_div(parent_rate, rate);
 
-	clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
-	ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
+	/*
+	* pdiv is mainly targeted for low freq results, while fdiv
+	* should be used for div <= 64. The other way round can
+	* lead to 'duty cycle' issues.
+	*/
+
+	if (div <= 64) {
+		clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
+		ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
+	} else {
+		clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
+		ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
+	}
 
 	return ret;
 }
-- 
1.9.1

[PATCH 1/4] clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate

[Mike Turquette]

Quoting Peter Griffin (2015-01-20 07:32:41)
> Debugging eMMC on upstream kernels it has been noticed that when the
> targetpack configures MMC0 clock to 200Mhz (required to switch to
> HS200) then everything works OK. However if the kernel sets the
> clock rate using clk_set_rate, then the eMMC card initialisation
> fails with timeouts. Lower clock speeds (the default being 50Mhz)
> work ok, but they we fail to get good eMMC transfer rates.
> 
> Looking through the vendor kernel clock driver reveals Giuseppe
> had already fixed this issue, but the patch hasn't made its way
> upstream.
> 
> The issue is fixed by changing the logic to manage the pdiv and
> fdiv divisors used for setting the rate inside the flexgen driver code.
> 
> Pdiv is mainly targeted for low freq results, while fdiv should be
> used for divs =< 64. The other way can lead to 'duty cycle'
> issues.
> 
> I have changed the original patch to keep the original behaviour
> in cases where the div is >64 which matches the original comment
> and patch description more closely. Although no clocks appear to hit
> this case currently when booting an upstream kernel.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>

Applied to clk-next.

Regards,
Mike

> ---
>  drivers/clk/st/clk-flexgen.c | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
> index 2282cef..3a484b3 100644
> --- a/drivers/clk/st/clk-flexgen.c
> +++ b/drivers/clk/st/clk-flexgen.c
> @@ -138,16 +138,27 @@ static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
>         struct flexgen *flexgen = to_flexgen(hw);
>         struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
>         struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
> -       unsigned long primary_div = 0;
> +       unsigned long div = 0;
>         int ret = 0;
>  
>         pdiv_hw->clk = hw->clk;
>         fdiv_hw->clk = hw->clk;
>  
> -       primary_div = clk_best_div(parent_rate, rate);
> +       div = clk_best_div(parent_rate, rate);
>  
> -       clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
> -       ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
> +       /*
> +       * pdiv is mainly targeted for low freq results, while fdiv
> +       * should be used for div <= 64. The other way round can
> +       * lead to 'duty cycle' issues.
> +       */
> +
> +       if (div <= 64) {
> +               clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
> +               ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
> +       } else {
> +               clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
> +               ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
> +       }
>  
>         return ret;
>  }
> -- 
> 1.9.1
> 

[PATCH 2/4] sdhci-st: Add support for stih407 family silicon.

[Peter Griffin]

This patch adds support for the extra registers found on
stih407 family silicon which has the flashSS subsystem.

This mainly consists of some extra glue registers which are
used to correctly configure the controller hardware.

This patch also adds support for UHS modes for eMMC. To allow
UHS HS200/SD104 modes to function correctly, due to the
tight timing constriants, and data tuning requirement support
for PVT independent delay management is also added. Two types
of delay management are supported, static delay management and
dynamic delay management (dynamic delay loop), this delay
management is only available on eMMC pads on stih410 and later
silicon.

Testing on stih410-b2120 board achieves the following speeds
with HS200 eMMC card.

max-frequency = 200Mhz
/dev/mmcblk0p1:
 Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec

max-frequency = 100Mhz
root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec

max-frequency = 50Mhz
root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

This is better than the 3.10 kernel which achieves 77.59 MB/sec
at 200Mhz clock (same board/soc/eMMC).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 351 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 343 insertions(+), 8 deletions(-)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 328f348..6a4f46c 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -1,7 +1,7 @@
 /*
  * Support for SDHCI on STMicroelectronics SoCs
  *
- * Copyright (C) 2014 STMicroelectronics Ltd
+ * Copyright (C) 2015 STMicroelectronics Ltd
  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  * Contributors: Peter Griffin <peter.griffin@linaro.org>
  *
@@ -23,9 +23,293 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <linux/mmc/host.h>
-
+#include <linux/reset.h>
 #include "sdhci-pltfm.h"
 
+struct st_mmc_platform_data {
+	struct  reset_control *rstc;
+	void __iomem *top_ioaddr;
+};
+
+/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
+
+#define	ST_MMC_CCONFIG_REG_1		0x400
+#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
+#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
+#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
+#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
+#define ST_MMC_CCONFIG_1_DEFAULT	\
+				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
+				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
+				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
+
+#define ST_MMC_CCONFIG_REG_2		0x404
+#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
+#define ST_MMC_CCONFIG_ADMA2		BIT(24)
+#define ST_MMC_CCONFIG_8BIT		BIT(20)
+#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
+#define  MAX_BLK_LEN_1024		1
+#define  MAX_BLK_LEN_2048		2
+#define BASE_CLK_FREQ_200		0xc8
+#define BASE_CLK_FREQ_100		0x64
+#define BASE_CLK_FREQ_50		0x32
+#define ST_MMC_CCONFIG_2_DEFAULT \
+	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
+	 ST_MMC_CCONFIG_8BIT | \
+	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
+
+#define ST_MMC_CCONFIG_REG_3			0x408
+#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
+#define ST_MMC_CCONFIG_64BIT			BIT(24)
+#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
+#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
+#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
+#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
+#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
+#define ST_MMC_CCONFIG_SDMA			BIT(0)
+#define ST_MMC_CCONFIG_3_DEFAULT	\
+			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
+			  ST_MMC_CCONFIG_3P3_VOLT		| \
+			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
+			  ST_MMC_CCONFIG_SDMA)
+
+#define ST_MMC_CCONFIG_REG_4	0x40c
+#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
+#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
+#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
+#define ST_MMC_CCONFIG_DDR50	BIT(8)
+#define ST_MMC_CCONFIG_SDR104	BIT(4)
+#define ST_MMC_CCONFIG_SDR50	BIT(0)
+#define ST_MMC_CCONFIG_4_DEFAULT	0
+
+#define ST_MMC_CCONFIG_REG_5		0x410
+#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
+#define RETUNING_TIMER_CNT_MAX		0xf
+#define ST_MMC_CCONFIG_5_DEFAULT	0
+
+/* I/O configuration for Arasan IP */
+#define	ST_MMC_GP_OUTPUT	0x450
+#define ST_MMC_GP_OUTPUT_CD	BIT(12)
+
+#define ST_MMC_STATUS_R		0x460
+
+#define ST_TOP_MMC_DLY_FIX_OFF(x)	(x - 0x8)
+
+/* TOP config registers to manage static and dynamic delay */
+#define	ST_TOP_MMC_TX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0x8)
+#define	ST_TOP_MMC_RX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0xc)
+/* MMC delay control register */
+#define	ST_TOP_MMC_DLY_CTRL			ST_TOP_MMC_DLY_FIX_OFF(0x18)
+#define	ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD	BIT(0)
+#define	ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL	BIT(1)
+#define	ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE	BIT(8)
+#define	ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE	BIT(9)
+#define	ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY	BIT(10)
+#define	ST_TOP_MMC_START_DLL_LOCK		BIT(11)
+
+/* register to provide the phase-shift value for DLL */
+#define	ST_TOP_MMC_TX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x1c)
+#define	ST_TOP_MMC_RX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x20)
+#define	ST_TOP_MMC_RX_CMD_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x24)
+
+/* phase shift delay on the tx clk 2.188ns */
+#define	ST_TOP_MMC_TX_DLL_STEP_DLY_VALID	0x6
+
+#define	ST_TOP_MMC_DLY_MAX			0xf
+
+#define ST_TOP_MMC_DYN_DLY_CONF	\
+		(ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE | \
+		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
+		 ST_TOP_MMC_START_DLL_LOCK)
+
+/*
+ * For clock speeds greater than 90MHz, we need to check that the
+ * DLL procedure has finished before switching to ultra-speed modes.
+ */
+#define	CLK_TO_CHECK_DLL_LOCK	90000000
+
+static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
+{
+	if (ioaddr) {
+		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
+		writel_relaxed(ST_TOP_MMC_DLY_MAX,
+				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
+	}
+}
+
+/**
+ * st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
+ * @np: dt device node.
+ * @host: sdhci host
+ * Description: this function is to configure the Arasan host controller.
+ * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
+ * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
+ * or eMMC4.3.  This has to be done before registering the sdhci host.
+ */
+static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct mmc_host *mhost = host->mmc;
+	u32 cconf2, cconf3, cconf4, cconf5;
+
+	if (!of_device_is_compatible(np, "st,sdhci-stih407"))
+		return;
+
+	cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
+	cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
+	cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
+	cconf5 = ST_MMC_CCONFIG_5_DEFAULT;
+
+	writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
+			host->ioaddr + ST_MMC_CCONFIG_REG_1);
+
+	/* Set clock frequency, default to 50MHz if max-frequency is not
+	 * provided */
+
+	switch (mhost->f_max) {
+	case 200000000:
+		clk_set_rate(pltfm_host->clk, mhost->f_max);
+		cconf2 |= BASE_CLK_FREQ_200;
+		break;
+	case 100000000:
+		clk_set_rate(pltfm_host->clk, mhost->f_max);
+		cconf2 |= BASE_CLK_FREQ_100;
+		break;
+	default:
+		clk_set_rate(pltfm_host->clk, 50000000);
+		cconf2 |= BASE_CLK_FREQ_50;
+	}
+
+	writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
+
+	if (mhost->caps & MMC_CAP_NONREMOVABLE)
+		cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
+	else
+		/* CARD _D ET_CTRL */
+		writel_relaxed(ST_MMC_GP_OUTPUT_CD,
+				host->ioaddr + ST_MMC_GP_OUTPUT);
+
+	if (mhost->caps & MMC_CAP_UHS_SDR50) {
+		/* use 1.8V */
+		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
+		cconf4 |= ST_MMC_CCONFIG_SDR50;
+		/* Use tuning */
+		cconf5 |= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
+		/* Max timeout for retuning */
+		cconf5 |= RETUNING_TIMER_CNT_MAX;
+	}
+
+	if (mhost->caps & MMC_CAP_UHS_SDR104) {
+		/*
+		 * SDR104 implies the HC can support HS200 mode, so
+		 * it's mandatory to use 1.8V
+		 */
+		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
+		cconf4 |= ST_MMC_CCONFIG_SDR104;
+		/* Max timeout for retuning */
+		cconf5 |= RETUNING_TIMER_CNT_MAX;
+	}
+
+	if (mhost->caps & MMC_CAP_UHS_DDR50)
+		cconf4 |= ST_MMC_CCONFIG_DDR50;
+
+	writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
+	writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
+	writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
+}
+
+static inline void st_mmcss_set_dll(void __iomem *ioaddr)
+{
+	if (ioaddr) {
+		writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
+			ioaddr + ST_TOP_MMC_DLY_CTRL);
+		writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
+			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
+	}
+}
+
+static int st_mmcss_lock_dll(void __iomem *ioaddr)
+{
+	unsigned long curr, value;
+	unsigned long finish = jiffies + HZ;
+
+	/* Checks if the DLL procedure is finished */
+	do {
+		curr = jiffies;
+		value = readl(ioaddr + ST_MMC_STATUS_R);
+		if (value & 0x1)
+			return 0;
+
+		cpu_relax();
+	} while (!time_after_eq(curr, finish));
+
+	return -EBUSY;
+}
+
+static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
+{
+	int ret = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+
+	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
+		st_mmcss_set_dll(pdata->top_ioaddr);
+		ret = st_mmcss_lock_dll(host->ioaddr);
+	}
+
+	return ret;
+}
+
+static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
+					unsigned int uhs)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	int ret = 0;
+
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	switch (uhs) {
+	/*
+	 * Set V18_EN -- UHS modes do not work without this.
+	 * does not change signaling voltage
+	 */
+
+	case MMC_TIMING_UHS_SDR12:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR25:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR50:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+		ret = sdhci_st_set_dll_for_clock(host);
+		break;
+	case MMC_TIMING_UHS_SDR104:
+	case MMC_TIMING_MMC_HS200:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+		ret =  sdhci_st_set_dll_for_clock(host);
+		break;
+	case MMC_TIMING_UHS_DDR50:
+	case MMC_TIMING_MMC_DDR52:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+		break;
+	}
+
+	if (ret)
+		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
+
+	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
+
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
 	u32 ret;
@@ -48,22 +332,32 @@ static const struct sdhci_ops sdhci_st_ops = {
 	.set_bus_width = sdhci_set_bus_width,
 	.read_l = sdhci_st_readl,
 	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
 };
 
 static const struct sdhci_pltfm_data sdhci_st_pdata = {
 	.ops = &sdhci_st_ops,
 	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
-	    SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		SDHCI_QUIRK_NO_HISPD_BIT,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+		SDHCI_QUIRK2_STOP_WITH_TC,
 };
 
-
 static int sdhci_st_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	struct sdhci_host *host;
+	struct st_mmc_platform_data *pdata;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct clk *clk;
 	int ret = 0;
 	u16 host_version;
+	struct resource *res;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
 
 	clk =  devm_clk_get(&pdev->dev, "mmc");
 	if (IS_ERR(clk)) {
@@ -71,6 +365,12 @@ static int sdhci_st_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 	}
 
+	pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(pdata->rstc))
+		pdata->rstc = NULL;
+	else
+		reset_control_deassert(pdata->rstc);
+
 	host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
 	if (IS_ERR(host)) {
 		dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
@@ -78,7 +378,6 @@ static int sdhci_st_probe(struct platform_device *pdev)
 	}
 
 	ret = mmc_of_parse(host->mmc);
-
 	if (ret) {
 		dev_err(&pdev->dev, "Failed mmc_of_parse\n");
 		return ret;
@@ -86,9 +385,22 @@ static int sdhci_st_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(clk);
 
+	/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "top-mmc-delay");
+	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pdata->top_ioaddr)) {
+		dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
+		pdata->top_ioaddr = NULL;
+	}
+
 	pltfm_host = sdhci_priv(host);
+	pltfm_host->priv = pdata;
 	pltfm_host->clk = clk;
 
+	/* Configure the Arasan HC inside the flashSS */
+	st_mmcss_cconfig(np, host);
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed sdhci_add_host\n");
@@ -117,10 +429,17 @@ static int sdhci_st_remove(struct platform_device *pdev)
 {
 	struct sdhci_host *host = platform_get_drvdata(pdev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	int ret;
 
 	clk_disable_unprepare(pltfm_host->clk);
 
-	return sdhci_pltfm_unregister(pdev);
+	ret = sdhci_pltfm_unregister(pdev);
+
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
+	return ret;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -128,12 +447,18 @@ static int sdhci_st_suspend(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-	int ret = sdhci_suspend_host(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	int ret;
 
+	ret = sdhci_suspend_host(host);
 	if (ret)
 		goto out;
 
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
 	clk_disable_unprepare(pltfm_host->clk);
+
 out:
 	return ret;
 }
@@ -142,10 +467,20 @@ static int sdhci_st_resume(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	struct device_node *np = dev->of_node;
+	int ret;
 
 	clk_prepare_enable(pltfm_host->clk);
 
-	return sdhci_resume_host(host);
+	if (pdata->rstc)
+		reset_control_deassert(pdata->rstc);
+
+	st_mmcss_cconfig(np, host);
+
+	ret = sdhci_resume_host(host);
+
+	return ret;
 }
 #endif
 
-- 
1.9.1

[PATCH 2/4] sdhci-st: Add support for stih407 family silicon.

[Ulf Hansson]

On 20 January 2015 at 16:32, Peter Griffin <peter.griffin@linaro.org> wrote:
> This patch adds support for the extra registers found on
> stih407 family silicon which has the flashSS subsystem.
>
> This mainly consists of some extra glue registers which are
> used to correctly configure the controller hardware.
>
> This patch also adds support for UHS modes for eMMC. To allow
> UHS HS200/SD104 modes to function correctly, due to the
> tight timing constriants, and data tuning requirement support
> for PVT independent delay management is also added. Two types
> of delay management are supported, static delay management and
> dynamic delay management (dynamic delay loop), this delay
> management is only available on eMMC pads on stih410 and later
> silicon.
>
> Testing on stih410-b2120 board achieves the following speeds
> with HS200 eMMC card.
>
> max-frequency = 200Mhz
> /dev/mmcblk0p1:
>  Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
>
> max-frequency = 100Mhz
> root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>  Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
>
> max-frequency = 50Mhz
> root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>  Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec
>
> This is better than the 3.10 kernel which achieves 77.59 MB/sec
> at 200Mhz clock (same board/soc/eMMC).
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>  drivers/mmc/host/sdhci-st.c | 351 +++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 343 insertions(+), 8 deletions(-)

Would it be possible to split this patch, I think it's easier to
review it in smaller pieces.

>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 328f348..6a4f46c 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -1,7 +1,7 @@
>  /*
>   * Support for SDHCI on STMicroelectronics SoCs
>   *
> - * Copyright (C) 2014 STMicroelectronics Ltd
> + * Copyright (C) 2015 STMicroelectronics Ltd
>   * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
>   * Contributors: Peter Griffin <peter.griffin@linaro.org>
>   *
> @@ -23,9 +23,293 @@
>  #include <linux/module.h>
>  #include <linux/err.h>
>  #include <linux/mmc/host.h>
> -
> +#include <linux/reset.h>
>  #include "sdhci-pltfm.h"
>
> +struct st_mmc_platform_data {

Please rename this to st_mmc_data. We don't want this driver to
support "platform data", since it use DT right. :-)

> +       struct  reset_control *rstc;
> +       void __iomem *top_ioaddr;
> +};
> +
> +/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
> +
> +#define        ST_MMC_CCONFIG_REG_1            0x400
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT        BIT(24)
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ        BIT(12)
> +#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT    BIT(8)
> +#define ST_MMC_CCONFIG_ASYNC_WAKEUP    BIT(0)
> +#define ST_MMC_CCONFIG_1_DEFAULT       \
> +                               ((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
> +                                (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
> +                                (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
> +
> +#define ST_MMC_CCONFIG_REG_2           0x404
> +#define ST_MMC_CCONFIG_HIGH_SPEED      BIT(28)
> +#define ST_MMC_CCONFIG_ADMA2           BIT(24)
> +#define ST_MMC_CCONFIG_8BIT            BIT(20)
> +#define ST_MMC_CCONFIG_MAX_BLK_LEN     16
> +#define  MAX_BLK_LEN_1024              1
> +#define  MAX_BLK_LEN_2048              2
> +#define BASE_CLK_FREQ_200              0xc8
> +#define BASE_CLK_FREQ_100              0x64
> +#define BASE_CLK_FREQ_50               0x32
> +#define ST_MMC_CCONFIG_2_DEFAULT \
> +       (ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
> +        ST_MMC_CCONFIG_8BIT | \
> +        (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
> +
> +#define ST_MMC_CCONFIG_REG_3                   0x408
> +#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE          BIT(28)
> +#define ST_MMC_CCONFIG_64BIT                   BIT(24)
> +#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT     BIT(20)
> +#define ST_MMC_CCONFIG_1P8_VOLT                        BIT(16)
> +#define ST_MMC_CCONFIG_3P0_VOLT                        BIT(12)
> +#define ST_MMC_CCONFIG_3P3_VOLT                        BIT(8)
> +#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT                BIT(4)
> +#define ST_MMC_CCONFIG_SDMA                    BIT(0)
> +#define ST_MMC_CCONFIG_3_DEFAULT       \
> +                        (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT    | \
> +                         ST_MMC_CCONFIG_3P3_VOLT               | \
> +                         ST_MMC_CCONFIG_SUSP_RES_SUPPORT       | \
> +                         ST_MMC_CCONFIG_SDMA)
> +
> +#define ST_MMC_CCONFIG_REG_4   0x40c
> +#define ST_MMC_CCONFIG_D_DRIVER        BIT(20)
> +#define ST_MMC_CCONFIG_C_DRIVER        BIT(16)
> +#define ST_MMC_CCONFIG_A_DRIVER        BIT(12)
> +#define ST_MMC_CCONFIG_DDR50   BIT(8)
> +#define ST_MMC_CCONFIG_SDR104  BIT(4)
> +#define ST_MMC_CCONFIG_SDR50   BIT(0)
> +#define ST_MMC_CCONFIG_4_DEFAULT       0
> +
> +#define ST_MMC_CCONFIG_REG_5           0x410
> +#define ST_MMC_CCONFIG_TUNING_FOR_SDR50        BIT(8)
> +#define RETUNING_TIMER_CNT_MAX         0xf
> +#define ST_MMC_CCONFIG_5_DEFAULT       0
> +
> +/* I/O configuration for Arasan IP */
> +#define        ST_MMC_GP_OUTPUT        0x450
> +#define ST_MMC_GP_OUTPUT_CD    BIT(12)
> +
> +#define ST_MMC_STATUS_R                0x460
> +
> +#define ST_TOP_MMC_DLY_FIX_OFF(x)      (x - 0x8)
> +
> +/* TOP config registers to manage static and dynamic delay */
> +#define        ST_TOP_MMC_TX_CLK_DLY                   ST_TOP_MMC_DLY_FIX_OFF(0x8)
> +#define        ST_TOP_MMC_RX_CLK_DLY                   ST_TOP_MMC_DLY_FIX_OFF(0xc)
> +/* MMC delay control register */
> +#define        ST_TOP_MMC_DLY_CTRL                     ST_TOP_MMC_DLY_FIX_OFF(0x18)
> +#define        ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD      BIT(0)
> +#define        ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL   BIT(1)
> +#define        ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE       BIT(8)
> +#define        ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE       BIT(9)
> +#define        ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY   BIT(10)
> +#define        ST_TOP_MMC_START_DLL_LOCK               BIT(11)
> +
> +/* register to provide the phase-shift value for DLL */
> +#define        ST_TOP_MMC_TX_DLL_STEP_DLY              ST_TOP_MMC_DLY_FIX_OFF(0x1c)
> +#define        ST_TOP_MMC_RX_DLL_STEP_DLY              ST_TOP_MMC_DLY_FIX_OFF(0x20)
> +#define        ST_TOP_MMC_RX_CMD_STEP_DLY              ST_TOP_MMC_DLY_FIX_OFF(0x24)
> +
> +/* phase shift delay on the tx clk 2.188ns */
> +#define        ST_TOP_MMC_TX_DLL_STEP_DLY_VALID        0x6
> +
> +#define        ST_TOP_MMC_DLY_MAX                      0xf
> +
> +#define ST_TOP_MMC_DYN_DLY_CONF        \
> +               (ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE | \
> +                ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
> +                ST_TOP_MMC_START_DLL_LOCK)
> +
> +/*
> + * For clock speeds greater than 90MHz, we need to check that the
> + * DLL procedure has finished before switching to ultra-speed modes.
> + */
> +#define        CLK_TO_CHECK_DLL_LOCK   90000000
> +
> +static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
> +{
> +       if (ioaddr) {
> +               writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
> +               writel_relaxed(ST_TOP_MMC_DLY_MAX,
> +                               ioaddr + ST_TOP_MMC_TX_CLK_DLY);
> +       }
> +}
> +
> +/**
> + * st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
> + * @np: dt device node.
> + * @host: sdhci host
> + * Description: this function is to configure the Arasan host controller.
> + * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
> + * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
> + * or eMMC4.3.  This has to be done before registering the sdhci host.
> + */
> +static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct mmc_host *mhost = host->mmc;
> +       u32 cconf2, cconf3, cconf4, cconf5;
> +
> +       if (!of_device_is_compatible(np, "st,sdhci-stih407"))
> +               return;

I think I would prefer to have this check done only once, during ->probe().

Such a check, would then need to handle assigning corresponding
function pointers/callbacks in the struct st_mmc_data, which is what
enables support for this feature.

Those functions pointers then needs to be validated before they are
invoked, of course.

> +
> +       cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
> +       cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
> +       cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
> +       cconf5 = ST_MMC_CCONFIG_5_DEFAULT;
> +
> +       writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
> +                       host->ioaddr + ST_MMC_CCONFIG_REG_1);
> +
> +       /* Set clock frequency, default to 50MHz if max-frequency is not
> +        * provided */
> +
> +       switch (mhost->f_max) {
> +       case 200000000:
> +               clk_set_rate(pltfm_host->clk, mhost->f_max);
> +               cconf2 |= BASE_CLK_FREQ_200;
> +               break;
> +       case 100000000:
> +               clk_set_rate(pltfm_host->clk, mhost->f_max);
> +               cconf2 |= BASE_CLK_FREQ_100;
> +               break;
> +       default:
> +               clk_set_rate(pltfm_host->clk, 50000000);
> +               cconf2 |= BASE_CLK_FREQ_50;
> +       }
> +
> +       writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
> +
> +       if (mhost->caps & MMC_CAP_NONREMOVABLE)
> +               cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
> +       else
> +               /* CARD _D ET_CTRL */
> +               writel_relaxed(ST_MMC_GP_OUTPUT_CD,
> +                               host->ioaddr + ST_MMC_GP_OUTPUT);
> +
> +       if (mhost->caps & MMC_CAP_UHS_SDR50) {
> +               /* use 1.8V */
> +               cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
> +               cconf4 |= ST_MMC_CCONFIG_SDR50;
> +               /* Use tuning */
> +               cconf5 |= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
> +               /* Max timeout for retuning */
> +               cconf5 |= RETUNING_TIMER_CNT_MAX;
> +       }
> +
> +       if (mhost->caps & MMC_CAP_UHS_SDR104) {
> +               /*
> +                * SDR104 implies the HC can support HS200 mode, so
> +                * it's mandatory to use 1.8V
> +                */
> +               cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
> +               cconf4 |= ST_MMC_CCONFIG_SDR104;
> +               /* Max timeout for retuning */
> +               cconf5 |= RETUNING_TIMER_CNT_MAX;
> +       }
> +
> +       if (mhost->caps & MMC_CAP_UHS_DDR50)
> +               cconf4 |= ST_MMC_CCONFIG_DDR50;
> +
> +       writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
> +       writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
> +       writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
> +}
> +
> +static inline void st_mmcss_set_dll(void __iomem *ioaddr)
> +{
> +       if (ioaddr) {
> +               writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
> +                       ioaddr + ST_TOP_MMC_DLY_CTRL);
> +               writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
> +                       ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
> +       }
> +}
> +
> +static int st_mmcss_lock_dll(void __iomem *ioaddr)
> +{
> +       unsigned long curr, value;
> +       unsigned long finish = jiffies + HZ;
> +
> +       /* Checks if the DLL procedure is finished */
> +       do {
> +               curr = jiffies;
> +               value = readl(ioaddr + ST_MMC_STATUS_R);
> +               if (value & 0x1)
> +                       return 0;
> +
> +               cpu_relax();
> +       } while (!time_after_eq(curr, finish));
> +
> +       return -EBUSY;
> +}
> +
> +static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
> +{
> +       int ret = 0;
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +
> +       if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
> +               st_mmcss_set_dll(pdata->top_ioaddr);
> +               ret = st_mmcss_lock_dll(host->ioaddr);
> +       }
> +
> +       return ret;
> +}
> +
> +static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
> +                                       unsigned int uhs)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +       u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> +       int ret = 0;
> +
> +       /* Select Bus Speed Mode for host */
> +       ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
> +       switch (uhs) {
> +       /*
> +        * Set V18_EN -- UHS modes do not work without this.
> +        * does not change signaling voltage
> +        */
> +
> +       case MMC_TIMING_UHS_SDR12:
> +               st_mmcss_set_static_delay(pdata->top_ioaddr);
> +               ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
> +               break;
> +       case MMC_TIMING_UHS_SDR25:
> +               st_mmcss_set_static_delay(pdata->top_ioaddr);
> +               ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
> +               break;
> +       case MMC_TIMING_UHS_SDR50:
> +               st_mmcss_set_static_delay(pdata->top_ioaddr);
> +               ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
> +               ret = sdhci_st_set_dll_for_clock(host);
> +               break;
> +       case MMC_TIMING_UHS_SDR104:
> +       case MMC_TIMING_MMC_HS200:
> +               st_mmcss_set_static_delay(pdata->top_ioaddr);
> +               ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
> +               ret =  sdhci_st_set_dll_for_clock(host);
> +               break;
> +       case MMC_TIMING_UHS_DDR50:
> +       case MMC_TIMING_MMC_DDR52:
> +               st_mmcss_set_static_delay(pdata->top_ioaddr);
> +               ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
> +               break;
> +       }
> +
> +       if (ret)
> +               dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
> +
> +       dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
> +
> +       sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> +}
> +
>  static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>  {
>         u32 ret;
> @@ -48,22 +332,32 @@ static const struct sdhci_ops sdhci_st_ops = {
>         .set_bus_width = sdhci_set_bus_width,
>         .read_l = sdhci_st_readl,
>         .reset = sdhci_reset,
> +       .set_uhs_signaling = sdhci_st_set_uhs_signaling,
>  };
>
>  static const struct sdhci_pltfm_data sdhci_st_pdata = {
>         .ops = &sdhci_st_ops,
>         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
> -           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +               SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> +               SDHCI_QUIRK_NO_HISPD_BIT,
> +       .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> +               SDHCI_QUIRK2_STOP_WITH_TC,
>  };
>
> -
>  static int sdhci_st_probe(struct platform_device *pdev)
>  {
> +       struct device_node *np = pdev->dev.of_node;
>         struct sdhci_host *host;
> +       struct st_mmc_platform_data *pdata;
>         struct sdhci_pltfm_host *pltfm_host;
>         struct clk *clk;
>         int ret = 0;
>         u16 host_version;
> +       struct resource *res;
> +
> +       pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +       if (!pdata)
> +               return -ENOMEM;
>
>         clk =  devm_clk_get(&pdev->dev, "mmc");
>         if (IS_ERR(clk)) {
> @@ -71,6 +365,12 @@ static int sdhci_st_probe(struct platform_device *pdev)
>                 return PTR_ERR(clk);
>         }
>
> +       pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
> +       if (IS_ERR(pdata->rstc))
> +               pdata->rstc = NULL;
> +       else
> +               reset_control_deassert(pdata->rstc);
> +
>         host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
>         if (IS_ERR(host)) {
>                 dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
> @@ -78,7 +378,6 @@ static int sdhci_st_probe(struct platform_device *pdev)
>         }
>
>         ret = mmc_of_parse(host->mmc);
> -
>         if (ret) {
>                 dev_err(&pdev->dev, "Failed mmc_of_parse\n");
>                 return ret;
> @@ -86,9 +385,22 @@ static int sdhci_st_probe(struct platform_device *pdev)
>
>         clk_prepare_enable(clk);
>
> +       /* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
> +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> +                                          "top-mmc-delay");
> +       pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(pdata->top_ioaddr)) {
> +               dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
> +               pdata->top_ioaddr = NULL;
> +       }
> +
>         pltfm_host = sdhci_priv(host);
> +       pltfm_host->priv = pdata;
>         pltfm_host->clk = clk;
>
> +       /* Configure the Arasan HC inside the flashSS */
> +       st_mmcss_cconfig(np, host);
> +
>         ret = sdhci_add_host(host);
>         if (ret) {
>                 dev_err(&pdev->dev, "Failed sdhci_add_host\n");
> @@ -117,10 +429,17 @@ static int sdhci_st_remove(struct platform_device *pdev)
>  {
>         struct sdhci_host *host = platform_get_drvdata(pdev);
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +       int ret;
>
>         clk_disable_unprepare(pltfm_host->clk);
>
> -       return sdhci_pltfm_unregister(pdev);
> +       ret = sdhci_pltfm_unregister(pdev);
> +
> +       if (pdata->rstc)
> +               reset_control_assert(pdata->rstc);
> +
> +       return ret;
>  }
>
>  #ifdef CONFIG_PM_SLEEP
> @@ -128,12 +447,18 @@ static int sdhci_st_suspend(struct device *dev)
>  {
>         struct sdhci_host *host = dev_get_drvdata(dev);
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> -       int ret = sdhci_suspend_host(host);
> +       struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +       int ret;
>
> +       ret = sdhci_suspend_host(host);
>         if (ret)
>                 goto out;
>
> +       if (pdata->rstc)
> +               reset_control_assert(pdata->rstc);
> +
>         clk_disable_unprepare(pltfm_host->clk);
> +
>  out:
>         return ret;
>  }
> @@ -142,10 +467,20 @@ static int sdhci_st_resume(struct device *dev)
>  {
>         struct sdhci_host *host = dev_get_drvdata(dev);
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +       struct device_node *np = dev->of_node;
> +       int ret;
>
>         clk_prepare_enable(pltfm_host->clk);
>
> -       return sdhci_resume_host(host);
> +       if (pdata->rstc)
> +               reset_control_deassert(pdata->rstc);
> +
> +       st_mmcss_cconfig(np, host);
> +
> +       ret = sdhci_resume_host(host);
> +
> +       return ret;
>  }
>  #endif
>
> --
> 1.9.1
>

Kind regards
Uffe

[PATCH 3/4] mmc: sdhci-st: Update ST SDHCI binding documentation.

[Peter Griffin]

This patch updates the binding information to reflect the
extra dt options which are now supported by the sdhci-st.c
driver which enable support for stih407 family silicon.

Stih410 SoC and later support UHS modes for eMMC, so the
driver now makes use of these common bindings. Examples
are provided for both eMMC (which has additional bindings)
and also sd slot for stih407.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 ++++++++++++++++++---
 1 file changed, 90 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
index 7527db4..18d950d 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
@@ -5,20 +5,62 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties
 used by the sdhci-st driver.
 
 Required properties:
-- compatible :  Must be "st,sdhci"
-- clock-names : Should be "mmc"
-                See: Documentation/devicetree/bindings/resource-names.txt
-- clocks :      Phandle of the clock used by the sdhci controler
-                See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- compatible:		Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
+			to set the internal glue logic used for configuring the MMC
+			subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
+			family).
+
+- clock-names:		Should be "mmc".
+			See: Documentation/devicetree/bindings/resource-names.txt
+- clocks:		Phandle to the clock.
+			See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+- interrupts:		One mmc interrupt should be described here.
+- interrupt-names:	Should be "mmcirq".
+
+- pinctrl-names:	A pinctrl state names "default" must be defined.
+- pinctrl-0:		Phandle referencing pin configuration of the sd/emmc controller.
+			See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+- reg:			This must provide the host controller base address and it can also
+			contain the FlashSS Top register for TX/RX delay used by the driver
+			to configure DLL inside the flashSS, if so reg-names must also be
+			specified.
 
 Optional properties:
-- non-removable: non-removable slot
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
-- bus-width: Number of data lines
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
+- reg-names:		Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
+			for eMMC on stih407 family silicon to configure DLL inside FlashSS.
+
+- non-removable:	Non-removable slot. Also used for configuring mmcss in STiH407 SoC
+			family.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- bus-width:		Number of data lines.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- max-frequency: 	Can be 200MHz, 100Mz or 50MHz (default) and used for
+			configuring the CCONFIG3 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- resets:		Phandle and reset specifier pair to softreset line of HC IP.
+			See: Documentation/devicetree/bindings/reset/reset.txt
+
+- vqmmc-supply:		Phandle to the regulator dt node, mentioned as the vcc/vdd
+			supply in eMMC/SD specs.
+
+- sd-uhs--sdr50:	To enable the SDR50 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- sd-uhs-sdr104:	To enable the SDR104 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- sd-uhs-ddr50:		To enable the DDR50 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
 
 Example:
 
+/* Example stih416e eMMC configuration */
+
 mmc0: sdhci at fe81e000 {
 	compatible	= "st,sdhci";
 	status		= "disabled";
@@ -29,5 +71,43 @@ mmc0: sdhci at fe81e000 {
 	pinctrl-0	= <&pinctrl_mmc0>;
 	clock-names	= "mmc";
 	clocks		= <&clk_s_a1_ls 1>;
-	bus-width       = <8>
+	bus-width	= <8>
+
+/* Example SD stih407 family configuration */
+
+mmc1: sdhci at 09080000 {
+	compatible	= "st,sdhci-stih407", "st,sdhci";
+	status		= "disabled";
+	reg		= <0x09080000 0x7ff>;
+	reg-names	= "mmc";
+	interrupts	= <GIC_SPI 90 IRQ_TYPE_NONE>;
+	interrupt-names	= "mmcirq";
+	pinctrl-names	= "default";
+	pinctrl-0	= <&pinctrl_sd1>;
+	clock-names	= "mmc";
+	clocks		= <&clk_s_c0_flexgen CLK_MMC_1>;
+	resets		= <&softreset STIH407_MMC1_SOFTRESET>;
+	bus-width	= <4>;
+};
+
+/* Example eMMC stih407 family configuration */
+
+mmc0: sdhci at 09060000 {
+	compatible	= "st,sdhci-stih407", "st,sdhci";
+	status		= "disabled";
+	reg		= <0x09060000 0x7ff>, <0x9061008 0x20>;
+	reg-names	= "mmc", "top-mmc-delay";
+	interrupts	= <GIC_SPI 92 IRQ_TYPE_NONE>;
+	interrupt-names	= "mmcirq";
+	pinctrl-names	= "default";
+	pinctrl-0	= <&pinctrl_mmc0>;
+	clock-names	= "mmc";
+	clocks		= <&clk_s_c0_flexgen CLK_MMC_0>;
+	vqmmc-supply	= <&vmmc_reg>;
+	max-frequency	= <200000000>;
+	bus-width	= <8>;
+	non-removable;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };
-- 
1.9.1

[PATCH 4/4] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Peter Griffin]

The nodes have been split to allow as much commonality as possible.
The stih407 has a silicon bug with eMMC UHS modes (with top regs)
and as such doesn't have any of the uhs dt properties.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
 arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
 3 files changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index d4a8f84..df0284b 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -283,5 +283,35 @@
 				 <&picophyreset STIH407_PICOPHY0_RESET>;
 			reset-names = "global", "port";
 		};
+
+		mmc0: sdhci at 09060000 {
+			compatible = "st,sdhci-stih407", "st,sdhci";
+			status = "disabled";
+			reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
+			reg-names = "mmc", "top-mmc-delay";
+			interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
+			interrupt-names = "mmcirq";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_mmc0>;
+			clock-names = "mmc";
+			clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+			bus-width = <8>;
+			non-removable;
+		};
+
+		mmc1: sdhci at 09080000 {
+			compatible = "st,sdhci-stih407", "st,sdhci";
+			status = "disabled";
+			reg = <0x09080000 0x7ff>;
+			reg-names = "mmc";
+			interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
+			interrupt-names = "mmcirq";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_sd1>;
+			clock-names = "mmc";
+			clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
+			resets = <&softreset STIH407_MMC1_SOFTRESET>;
+			bus-width = <4>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 2f61a99..16f02c5 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -26,4 +26,14 @@
 	aliases {
 		ttyAS0 = &sbc_serial0;
 	};
+
+	soc {
+
+		mmc0: sdhci at 09060000 {
+			max-frequency = <200000000>;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			sd-uhs-ddr50;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 0074bd4..19082ed 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -47,6 +47,14 @@
 			status = "okay";
 		};
 
+		mmc0: sdhci at 09060000 {
+			status = "okay";
+		};
+
+		mmc1: sdhci at 09080000 {
+			status = "okay";
+		};
+
 		/* SSC11 to HDMI */
 		i2c at 9541000 {
 			status = "okay";
-- 
1.9.1