[PATCH 0/6] Add support for QCOM GDSCs

[PATCH 0/6] Add support for QCOM GDSCs

[Rajendra Nayak]

GDSCs (Global Distributed Switch Controllers) control switches
that supply power to an on-chip power domain and hence can be
programmed in SW to safely power collapse and restore power to the
respective PDs. They are part of a considerable number of recent QCOM
SoCs (This series adds support for msm8974, msm8916 and apq8084 devices)
and are part of the Clock control block.

The series implements support for GDSC using the genpd framework
modelling these as SW controllable power domains.

8916 support has a dependency on the Global Clock controller support [1]
posted by Georgi Djakov.

[1] 
https://lkml.org/lkml/2015/2/25/416

Rajendra Nayak (3):
  clk: qcom: gdsc: Prepare common clk probe to register gdscs
  clk: qcom: gdsc: Add GDSCs in msm8916 GCC
  clk: qcom: gdsc: Add GDSCs in apq8084 GCC

Stephen Boyd (3):
  clk: qcom: Add support for GDSCs
  clk: qcom: gdsc: Add GDSCs in msm8974 GCC
  clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

 drivers/clk/qcom/Kconfig                      |   8 ++
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/common.c                     |  27 +++++-
 drivers/clk/qcom/common.h                     |   2 +
 drivers/clk/qcom/gcc-apq8084.c                |  38 ++++++++
 drivers/clk/qcom/gcc-msm8916.c                |  46 +++++++++
 drivers/clk/qcom/gcc-msm8974.c                |  14 +++
 drivers/clk/qcom/gdsc.c                       | 130 ++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h                       |  43 +++++++++
 drivers/clk/qcom/mmcc-msm8974.c               |  54 +++++++++++
 include/dt-bindings/clock/qcom,gcc-apq8084.h  |   6 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h  |   8 ++
 include/dt-bindings/clock/qcom,gcc-msm8974.h  |   3 +
 include/dt-bindings/clock/qcom,mmcc-msm8974.h |   8 ++
 14 files changed, 387 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 1/6] clk: qcom: Add support for GDSCs

[Rajendra Nayak]

From: Stephen Boyd <sboyd@codeaurora.org>

GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/Kconfig  |   5 ++
 drivers/clk/qcom/Makefile |   1 +
 drivers/clk/qcom/gdsc.c   | 130 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h   |  43 +++++++++++++++
 4 files changed, 179 insertions(+)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 48d5151..f436bcf 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -38,6 +38,11 @@ config IPQ_LCC_806X
 	  Say Y if you want to use audio devices such as i2s, pcm,
 	  S/PDIF, etc.
 
+config QCOM_GDSC
+	bool
+	select PM_GENERIC_DOMAINS if PM
+	depends on COMMON_CLK_QCOM
+
 config MSM_GCC_8660
 	tristate "MSM8660 Global Clock Controller"
 	depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 50b337a..fe62523 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += reset.o
+clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
new file mode 100644
index 0000000..c1dd762
--- /dev/null
+++ b/drivers/clk/qcom/gdsc.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/pm_domain.h>
+#include <linux/regmap.h>
+#include <linux/jiffies.h>
+#include <linux/export.h>
+
+#include "gdsc.h"
+
+#define PWR_ON_MASK		BIT(31)
+#define EN_REST_WAIT_MASK	(0xF << 20)
+#define EN_FEW_WAIT_MASK	(0xF << 16)
+#define CLK_DIS_WAIT_MASK	(0xF << 12)
+#define SW_OVERRIDE_MASK	BIT(2)
+#define HW_CONTROL_MASK		BIT(1)
+#define SW_COLLAPSE_MASK	BIT(0)
+
+/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
+#define EN_REST_WAIT_VAL	(0x2 << 20)
+#define EN_FEW_WAIT_VAL		(0x8 << 16)
+#define CLK_DIS_WAIT_VAL	(0x2 << 12)
+
+#define TIMEOUT_US		100
+
+static int gdsc_is_enabled(struct gdsc *sc)
+{
+	u32 val;
+
+	regmap_read(sc->regmap, sc->gdscr, &val);
+	return !!(val & PWR_ON_MASK);
+}
+
+static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+{
+	int ret;
+	u32 val = en ? 0 : SW_COLLAPSE_MASK;
+	u32 check = en ? PWR_ON_MASK : 0;
+	unsigned long timeout;
+
+	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
+	if (ret)
+		return ret;
+
+	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+	do {
+		regmap_read(sc->regmap, sc->gdscr, &val);
+		if ((val & PWR_ON_MASK) == check)
+			return 0;
+	} while (time_before(jiffies, timeout));
+	regmap_read(sc->regmap, sc->gdscr, &val);
+	if ((val & PWR_ON_MASK) == check)
+		return 0;
+
+	pr_err("%s %s timed out\n", en ? "enabling" : "disabling", sc->pd.name);
+	return -ETIMEDOUT;
+}
+
+static int gdsc_enable(struct generic_pm_domain *domain)
+{
+	struct gdsc *sc = domain_to_gdsc(domain);
+	int ret;
+
+	ret = gdsc_toggle_logic(sc, true);
+	if (ret)
+		return ret;
+	/*
+	 * If clocks to this power domain were already on, they will take an
+	 * additional 4 clock cycles to re-enable after the power domain is
+	 * enabled. Delay to account for this. A delay is also needed to ensure
+	 * clocks are not enabled within 400ns of enabling power to the
+	 * memories.
+	 */
+	udelay(1);
+
+	return 0;
+}
+
+static int gdsc_disable(struct generic_pm_domain *domain)
+{
+	struct gdsc *sc = domain_to_gdsc(domain);
+	int ret = 0;
+
+	ret = gdsc_toggle_logic(sc, false);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+int gdsc_init(struct generic_pm_domain *domain, struct regmap *regmap)
+{
+	struct gdsc *sc = domain_to_gdsc(domain);
+	u32 mask;
+	u32 val;
+	int on;
+
+	sc->regmap = regmap;
+
+	/*
+	 * Disable HW trigger: collapse/restore occur based on registers writes.
+	 * Disable SW override: Use hardware state-machine for sequencing.
+	 * Configure wait time between states.
+	 */
+	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
+	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
+	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
+	regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
+
+	on = gdsc_is_enabled(sc);
+
+	pm_genpd_init(&sc->pd, NULL, !on);
+	sc->pd.power_off = gdsc_disable;
+	sc->pd.power_on = gdsc_enable;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(gdsc_init);
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
new file mode 100644
index 0000000..82a26d9
--- /dev/null
+++ b/drivers/clk/qcom/gdsc.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+
+struct regmap;
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * pd: power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+	struct generic_pm_domain	pd;
+	struct regmap			*regmap;
+	unsigned int			gdscr;
+};
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_init(struct generic_pm_domain *domain, struct regmap *regmap);
+#else
+int gdsc_init(struct generic_pm_domain *domain, struct regmap *regmap)
+{
+	return 0;
+}
+#endif /* CONFIG_QCOM_GDSC */
+#endif /* __QCOM_GDSC_H__ */
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 2/6] clk: qcom: gdsc: Prepare common clk probe to register gdscs

[Rajendra Nayak]

The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/common.c | 27 ++++++++++++++++++++++++++-
 drivers/clk/qcom/common.h |  2 ++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index e20d947..d5b65fa 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -21,10 +21,12 @@
 #include "clk-rcg.h"
 #include "clk-regmap.h"
 #include "reset.h"
+#include "gdsc.h"
 
 struct qcom_cc {
 	struct qcom_reset_controller reset;
 	struct clk_onecell_data data;
+	struct genpd_onecell_data pd_data;
 	struct clk *clks[];
 };
 
@@ -66,10 +68,12 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 	struct device *dev = &pdev->dev;
 	struct clk *clk;
 	struct clk_onecell_data *data;
+	struct genpd_onecell_data *pd;
 	struct clk **clks;
 	struct qcom_reset_controller *reset;
 	struct qcom_cc *cc;
 	size_t num_clks = desc->num_clks;
+	size_t num_gdscs = desc->num_gdscs;
 	struct clk_regmap **rclks = desc->clks;
 
 	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
@@ -79,8 +83,11 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 
 	clks = cc->clks;
 	data = &cc->data;
+	pd = &cc->pd_data;
 	data->clks = clks;
 	data->clk_num = num_clks;
+	pd->domains = desc->gdscs;
+	pd->num_domains = num_gdscs;
 
 	for (i = 0; i < num_clks; i++) {
 		if (!rclks[i]) {
@@ -108,8 +115,25 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 
 	ret = reset_controller_register(&reset->rcdev);
 	if (ret)
-		of_clk_del_provider(dev->of_node);
+		goto err_reset;
 
+	if (num_gdscs) {
+		for (i = 0; i < num_gdscs; i++) {
+			if (!desc->gdscs[i])
+				continue;
+			gdsc_init(desc->gdscs[i], regmap);
+		}
+
+		ret = of_genpd_add_provider_onecell(dev->of_node, pd);
+		if (ret)
+			goto err_pd;
+	}
+
+	return 0;
+err_pd:
+	reset_controller_unregister(&reset->rcdev);
+err_reset:
+	of_clk_del_provider(dev->of_node);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
@@ -128,6 +152,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);
 
 void qcom_cc_remove(struct platform_device *pdev)
 {
+	of_genpd_del_provider(pdev->dev.of_node);
 	of_clk_del_provider(pdev->dev.of_node);
 	reset_controller_unregister(platform_get_drvdata(pdev));
 }
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index f519322..55e69c5 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -26,6 +26,8 @@ struct qcom_cc_desc {
 	size_t num_clks;
 	const struct qcom_reset_map *resets;
 	size_t num_resets;
+	struct generic_pm_domain **gdscs;
+	size_t num_gdscs;
 };
 
 extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 3/6] clk: qcom: gdsc: Add GDSCs in msm8916 GCC

[Rajendra Nayak]

Add all data for the GDSCs which are part of msm8916 GCC block.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/Kconfig                     |  1 +
 drivers/clk/qcom/gcc-msm8916.c               | 46 ++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |  8 +++++
 3 files changed, 55 insertions(+)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index f436bcf..2fe1b30 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -53,6 +53,7 @@ config MSM_GCC_8660
 
 config MSM_GCC_8916
 	tristate "MSM8916 Global Clock Controller"
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the global clock controller on msm8916 devices.
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 810c380..7cda302 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define P_XO			0
 #define P_GPLL0			1
@@ -2560,6 +2561,41 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
 	},
 };
 
+static struct gdsc venus_gdsc = {
+	.gdscr = 0x4c018,
+	.pd = {
+		.name = "venus",
+	},
+};
+
+static struct gdsc mdss_gdsc = {
+	.gdscr = 0x4d078,
+	.pd = {
+		.name = "mdss",
+	},
+};
+
+static struct gdsc jpeg_gdsc = {
+	.gdscr = 0x5701c,
+	.pd = {
+		.name = "jpeg",
+	},
+};
+
+static struct gdsc vfe_gdsc = {
+	.gdscr = 0x58034,
+	.pd = {
+		.name = "vfe",
+	},
+};
+
+static struct gdsc oxili_gdsc = {
+	.gdscr = 0x5901c,
+	.pd = {
+		.name = "oxili",
+	},
+};
+
 static struct clk_regmap *gcc_msm8916_clocks[] = {
 	[GPLL0] = &gpll0.clkr,
 	[GPLL0_VOTE] = &gpll0_vote,
@@ -2701,6 +2737,14 @@ static struct clk_regmap *gcc_msm8916_clocks[] = {
 	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
 };
 
+static struct generic_pm_domain *gcc_msm8916_gdscs[] = {
+	[VENUS_GDSC] = &venus_gdsc.pd,
+	[MDSS_GDSC] = &mdss_gdsc.pd,
+	[JPEG_GDSC] = &jpeg_gdsc.pd,
+	[VFE_GDSC] = &vfe_gdsc.pd,
+	[OXILI_GDSC] = &oxili_gdsc.pd,
+};
+
 static const struct qcom_reset_map gcc_msm8916_resets[] = {
 	[GCC_BLSP1_BCR] = { 0x01000 },
 	[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
@@ -2808,6 +2852,8 @@ static const struct qcom_cc_desc gcc_msm8916_desc = {
 	.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
 	.resets = gcc_msm8916_resets,
 	.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
+	.gdscs = gcc_msm8916_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
 };
 
 static const struct of_device_id gcc_msm8916_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index e430f64..11566c5 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -153,4 +153,12 @@
 #define GCC_VENUS0_AXI_CLK			136
 #define GCC_VENUS0_VCODEC0_CLK			137
 
+/* Indexes for GDSCs */
+#define BIMC_GDSC				0
+#define VENUS_GDSC				1
+#define MDSS_GDSC				2
+#define JPEG_GDSC				3
+#define VFE_GDSC				4
+#define OXILI_GDSC				5
+
 #endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 4/6] clk: qcom: gdsc: Add GDSCs in msm8974 GCC

[Rajendra Nayak]

From: Stephen Boyd <sboyd@codeaurora.org>

Theres just one GDSC as part of the msm8974 GCC block.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/Kconfig                     |  1 +
 drivers/clk/qcom/gcc-msm8974.c               | 14 ++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8974.h |  3 +++
 3 files changed, 18 insertions(+)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 2fe1b30..77568bd 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -88,6 +88,7 @@ config MSM_MMCC_8960
 
 config MSM_GCC_8974
 	tristate "MSM8974 Global Clock Controller"
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the global clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index a6937fe..b20b19d 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define P_XO	0
 #define P_GPLL0	1
@@ -2429,6 +2430,13 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
 	},
 };
 
+static struct gdsc usb_hs_hsic_gdsc = {
+	.gdscr = 0x404,
+	.pd = {
+		.name = "usb_hs_hsic",
+	},
+};
+
 static struct clk_regmap *gcc_msm8974_clocks[] = {
 	[GPLL0] = &gpll0.clkr,
 	[GPLL0_VOTE] = &gpll0_vote,
@@ -2658,6 +2666,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = {
 	[GCC_VENUS_RESTART] = { 0x1740 },
 };
 
+static struct generic_pm_domain *gcc_msm8974_gdscs[] = {
+	[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc.pd,
+};
+
 static const struct regmap_config gcc_msm8974_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -2672,6 +2684,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
 	.num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
 	.resets = gcc_msm8974_resets,
 	.num_resets = ARRAY_SIZE(gcc_msm8974_resets),
+	.gdscs = gcc_msm8974_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
 };
 
 static const struct of_device_id gcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
index 51e51c8..81d32f6 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -321,4 +321,7 @@
 #define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
 #define GCC_SDCC1_CDCCAL_FF_CLK					305
 
+/* gdscs */
+#define USB_HS_HSIC_GDSC					0
+
 #endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 5/6] clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

[Rajendra Nayak]

From: Stephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of msm8974 MMCC block

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/Kconfig                      |  1 +
 drivers/clk/qcom/mmcc-msm8974.c               | 54 +++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,mmcc-msm8974.h |  8 ++++
 3 files changed, 63 insertions(+)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 77568bd..104ec0c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -98,6 +98,7 @@ config MSM_GCC_8974
 config MSM_MMCC_8974
 	tristate "MSM8974 Multimedia Clock Controller"
 	select MSM_GCC_8974
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the multimedia clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index be94c54..c7af21d 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define P_XO		0
 #define P_MMPLL0	1
@@ -2347,6 +2348,48 @@ static struct pll_config mmpll3_config = {
 	.aux_output_mask = BIT(1),
 };
 
+static struct gdsc venus0_gdsc = {
+	.gdscr = 0x1024,
+	.pd = {
+		.name = "venus0",
+	},
+};
+
+static struct gdsc mdss_gdsc = {
+	.gdscr = 0x2304,
+	.pd = {
+		.name = "mdss",
+	},
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+	.gdscr = 0x35a4,
+	.pd = {
+		.name = "camss_jpeg",
+	},
+};
+
+static struct gdsc camss_vfe_gdsc = {
+	.gdscr = 0x36a4,
+	.pd = {
+		.name = "camss_vfe",
+	},
+};
+
+static struct gdsc oxili_gdsc = {
+	.gdscr = 0x4024,
+	.pd = {
+		.name = "oxili",
+	},
+};
+
+static struct gdsc oxilicx_gdsc = {
+	.gdscr = 0x4034,
+	.pd = {
+		.name = "oxilicx",
+	},
+};
+
 static struct clk_regmap *mmcc_msm8974_clocks[] = {
 	[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
 	[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -2523,6 +2566,15 @@ static const struct qcom_reset_map mmcc_msm8974_resets[] = {
 	[OCMEMNOC_RESET] = { 0x50b0 },
 };
 
+static struct generic_pm_domain *mmcc_msm8974_gdscs[] = {
+	[VENUS0_GDSC] = &venus0_gdsc.pd,
+	[MDSS_GDSC] = &mdss_gdsc.pd,
+	[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc.pd,
+	[CAMSS_VFE_GDSC] = &camss_vfe_gdsc.pd,
+	[OXILI_GDSC] = &oxili_gdsc.pd,
+	[OXILICX_GDSC] = &oxilicx_gdsc.pd,
+};
+
 static const struct regmap_config mmcc_msm8974_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -2537,6 +2589,8 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = {
 	.num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
 	.resets = mmcc_msm8974_resets,
 	.num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
+	.gdscs = mmcc_msm8974_gdscs,
+	.num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
 };
 
 static const struct of_device_id mmcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
index 032ed87..28651e5 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -158,4 +158,12 @@
 #define SPDM_RM_AXI					141
 #define SPDM_RM_OCMEMNOC				142
 
+/* gdscs */
+#define VENUS0_GDSC					0
+#define MDSS_GDSC					1
+#define CAMSS_JPEG_GDSC					2
+#define CAMSS_VFE_GDSC					3
+#define OXILI_GDSC					4
+#define OXILICX_GDSC					5
+
 #endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 6/6] clk: qcom: gdsc: Add GDSCs in apq8084 GCC

[Rajendra Nayak]

Add the GDSC instances that exist as part of apq8084 GCC block

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/gcc-apq8084.c               | 38 ++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-apq8084.h |  6 +++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index e3ef902..ccab028 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define P_XO	0
 #define P_GPLL0	1
@@ -3251,6 +3252,34 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
 	},
 };
 
+static struct gdsc usb_hs_hsic_gdsc = {
+	.gdscr = 0x404,
+	.pd = {
+		.name = "usb_hs_hsic",
+	},
+};
+
+static struct gdsc pcie0_gdsc = {
+	.gdscr = 0x1ac4,
+	.pd = {
+		.name = "pcie0",
+	},
+};
+
+static struct gdsc pcie1_gdsc = {
+	.gdscr = 0x1b44,
+	.pd = {
+		.name = "pcie1",
+	},
+};
+
+static struct gdsc usb30_gdsc = {
+	.gdscr = 0x1e84,
+	.pd = {
+		.name = "usb30",
+	},
+};
+
 static struct clk_regmap *gcc_apq8084_clocks[] = {
 	[GPLL0] = &gpll0.clkr,
 	[GPLL0_VOTE] = &gpll0_vote,
@@ -3444,6 +3473,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
 	[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
 };
 
+static struct generic_pm_domain *gcc_apq8084_gdscs[] = {
+	[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc.pd,
+	[PCIE0_GDSC] = &pcie0_gdsc.pd,
+	[PCIE1_GDSC] = &pcie1_gdsc.pd,
+	[USB30_GDSC] = &usb30_gdsc.pd,
+};
+
 static const struct qcom_reset_map gcc_apq8084_resets[] = {
 	[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
 	[GCC_CONFIG_NOC_BCR] = { 0x0140 },
@@ -3552,6 +3588,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = {
 	.num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
 	.resets = gcc_apq8084_resets,
 	.num_resets = ARRAY_SIZE(gcc_apq8084_resets),
+	.gdscs = gcc_apq8084_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
 };
 
 static const struct of_device_id gcc_apq8084_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
index 2c0da56..5aa7ebe 100644
--- a/include/dt-bindings/clock/qcom,gcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -348,4 +348,10 @@
 #define GCC_PCIE_1_PIPE_CLK				331
 #define GCC_PCIE_1_SLV_AXI_CLK				332
 
+/* gdscs */
+#define USB_HS_HSIC_GDSC				0
+#define PCIE0_GDSC					1
+#define PCIE1_GDSC					2
+#define USB30_GDSC					3
+
 #endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 1/6] clk: qcom: Add support for GDSCs

[Stanimir Varbanov]

On 03/02/2015 09:02 AM, Rajendra Nayak wrote:
> From: Stephen Boyd <sboyd@codeaurora.org>
> 
> GDSCs (Global Distributed Switch Controllers) are responsible for
> safely collapsing and restoring power to peripherals in the SoC.
> These are best modelled as power domains using genpd and given
> the registers are scattered throughout the clock controller register
> space, its best to have the support added through the clock driver.
> 
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
>  drivers/clk/qcom/Kconfig  |   5 ++
>  drivers/clk/qcom/Makefile |   1 +
>  drivers/clk/qcom/gdsc.c   | 130 ++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/qcom/gdsc.h   |  43 +++++++++++++++
>  4 files changed, 179 insertions(+)
>  create mode 100644 drivers/clk/qcom/gdsc.c
>  create mode 100644 drivers/clk/qcom/gdsc.h
> 

<snip>

> --- /dev/null
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -0,0 +1,130 @@
> +/*

<snip>

> +
> +#include "gdsc.h"
> +
> +#define PWR_ON_MASK		BIT(31)
> +#define EN_REST_WAIT_MASK	(0xF << 20)

you can use GENMASK(23, 20) here and below

> +#define EN_FEW_WAIT_MASK	(0xF << 16)
> +#define CLK_DIS_WAIT_MASK	(0xF << 12)
> +#define SW_OVERRIDE_MASK	BIT(2)
> +#define HW_CONTROL_MASK		BIT(1)
> +#define SW_COLLAPSE_MASK	BIT(0)
> +
> +/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
> +#define EN_REST_WAIT_VAL	(0x2 << 20)
> +#define EN_FEW_WAIT_VAL		(0x8 << 16)
> +#define CLK_DIS_WAIT_VAL	(0x2 << 12)
> +
> +#define TIMEOUT_US		100
> +
> +static int gdsc_is_enabled(struct gdsc *sc)
> +{
> +	u32 val;
> +
> +	regmap_read(sc->regmap, sc->gdscr, &val);

please, check the regmap_read for error, here and on few places below.

> +	return !!(val & PWR_ON_MASK);
> +}
> +
> +static int gdsc_toggle_logic(struct gdsc *sc, bool en)
> +{
> +	int ret;
> +	u32 val = en ? 0 : SW_COLLAPSE_MASK;
> +	u32 check = en ? PWR_ON_MASK : 0;
> +	unsigned long timeout;
> +
> +	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
> +	if (ret)
> +		return ret;
> +
> +	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
> +	do {
> +		regmap_read(sc->regmap, sc->gdscr, &val);
> +		if ((val & PWR_ON_MASK) == check)
> +			return 0;
> +	} while (time_before(jiffies, timeout));

blank line here will be better.

> +	regmap_read(sc->regmap, sc->gdscr, &val);
> +	if ((val & PWR_ON_MASK) == check)
> +		return 0;
> +
> +	pr_err("%s %s timed out\n", en ? "enabling" : "disabling", sc->pd.name);

use dev_err() or giving the error to the upper layers should be enough.

> +	return -ETIMEDOUT;
> +}
> +
> +static int gdsc_enable(struct generic_pm_domain *domain)
> +{
> +	struct gdsc *sc = domain_to_gdsc(domain);
> +	int ret;
> +
> +	ret = gdsc_toggle_logic(sc, true);
> +	if (ret)
> +		return ret;
> +	/*
> +	 * If clocks to this power domain were already on, they will take an
> +	 * additional 4 clock cycles to re-enable after the power domain is
> +	 * enabled. Delay to account for this. A delay is also needed to ensure
> +	 * clocks are not enabled within 400ns of enabling power to the
> +	 * memories.
> +	 */
> +	udelay(1);
> +
> +	return 0;
> +}
> +
> +static int gdsc_disable(struct generic_pm_domain *domain)
> +{
> +	struct gdsc *sc = domain_to_gdsc(domain);
> +	int ret = 0;
> +
> +	ret = gdsc_toggle_logic(sc, false);
> +	if (ret)
> +		return ret;
> +
> +	return ret;

return gdsc_toggle_logic(sc, false);

> +}
> +
> +int gdsc_init(struct generic_pm_domain *domain, struct regmap *regmap)
> +{
> +	struct gdsc *sc = domain_to_gdsc(domain);
> +	u32 mask;
> +	u32 val;
> +	int on;
> +
> +	sc->regmap = regmap;
> +
> +	/*
> +	 * Disable HW trigger: collapse/restore occur based on registers writes.
> +	 * Disable SW override: Use hardware state-machine for sequencing.
> +	 * Configure wait time between states.
> +	 */
> +	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
> +	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
> +	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
> +	regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
> +
> +	on = gdsc_is_enabled(sc);
> +
> +	pm_genpd_init(&sc->pd, NULL, !on);
> +	sc->pd.power_off = gdsc_disable;
> +	sc->pd.power_on = gdsc_enable;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(gdsc_init);

gdsc_init is used in common.c, no need to export it.

<snip>

-- 
regards,
Stan

[PATCH 2/6] clk: qcom: gdsc: Prepare common clk probe to register gdscs

[Stanimir Varbanov]

On 03/02/2015 09:02 AM, Rajendra Nayak wrote:
> The common clk probe registers a clk provider and a reset controller.
> Update it to register a genpd provider using the gdsc data provided
> by each platform.
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
>  drivers/clk/qcom/common.c | 27 ++++++++++++++++++++++++++-
>  drivers/clk/qcom/common.h |  2 ++
>  2 files changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
> index e20d947..d5b65fa 100644
> --- a/drivers/clk/qcom/common.c
> +++ b/drivers/clk/qcom/common.c
> @@ -21,10 +21,12 @@
>  #include "clk-rcg.h"
>  #include "clk-regmap.h"
>  #include "reset.h"
> +#include "gdsc.h"
>  
>  struct qcom_cc {
>  	struct qcom_reset_controller reset;
>  	struct clk_onecell_data data;
> +	struct genpd_onecell_data pd_data;

IMO this pd_data belongs to struct gdsc ...

>  	struct clk *clks[];
>  };
>  
> @@ -66,10 +68,12 @@ int qcom_cc_really_probe(struct platform_device *pdev,
>  	struct device *dev = &pdev->dev;
>  	struct clk *clk;
>  	struct clk_onecell_data *data;
> +	struct genpd_onecell_data *pd;
>  	struct clk **clks;
>  	struct qcom_reset_controller *reset;
>  	struct qcom_cc *cc;
>  	size_t num_clks = desc->num_clks;
> +	size_t num_gdscs = desc->num_gdscs;
>  	struct clk_regmap **rclks = desc->clks;
>  
>  	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
> @@ -79,8 +83,11 @@ int qcom_cc_really_probe(struct platform_device *pdev,
>  
>  	clks = cc->clks;
>  	data = &cc->data;
> +	pd = &cc->pd_data;
>  	data->clks = clks;
>  	data->clk_num = num_clks;
> +	pd->domains = desc->gdscs;
> +	pd->num_domains = num_gdscs;
>  
>  	for (i = 0; i < num_clks; i++) {
>  		if (!rclks[i]) {
> @@ -108,8 +115,25 @@ int qcom_cc_really_probe(struct platform_device *pdev,
>  
>  	ret = reset_controller_register(&reset->rcdev);
>  	if (ret)
> -		of_clk_del_provider(dev->of_node);
> +		goto err_reset;
>  
> +	if (num_gdscs) {
> +		for (i = 0; i < num_gdscs; i++) {
> +			if (!desc->gdscs[i])
> +				continue;
> +			gdsc_init(desc->gdscs[i], regmap);
> +		}
> +
> +		ret = of_genpd_add_provider_onecell(dev->of_node, pd);
> +		if (ret)
> +			goto err_pd;
> +	}

... and this code snippet should be moved in new gdsc_register()
function located in gdsc.c ...

> +
> +	return 0;
> +err_pd:
> +	reset_controller_unregister(&reset->rcdev);
> +err_reset:
> +	of_clk_del_provider(dev->of_node);
>  	return ret;
>  }
>  EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
> @@ -128,6 +152,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);
>  
>  void qcom_cc_remove(struct platform_device *pdev)
>  {
> +	of_genpd_del_provider(pdev->dev.of_node);
>  	of_clk_del_provider(pdev->dev.of_node);
>  	reset_controller_unregister(platform_get_drvdata(pdev));
>  }
> diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
> index f519322..55e69c5 100644
> --- a/drivers/clk/qcom/common.h
> +++ b/drivers/clk/qcom/common.h
> @@ -26,6 +26,8 @@ struct qcom_cc_desc {
>  	size_t num_clks;
>  	const struct qcom_reset_map *resets;
>  	size_t num_resets;
> +	struct generic_pm_domain **gdscs;

... and also replace struct generic_pm_domain with struct gdsc. This way
we will have the same abstraction level as reset controller?

> +	size_t num_gdscs;
>  };

<snip>

-- 
regards,
Stan

[PATCH 0/6] Add support for QCOM GDSCs

[Stanimir Varbanov]

On 03/02/2015 09:02 AM, Rajendra Nayak wrote:
> GDSCs (Global Distributed Switch Controllers) control switches
> that supply power to an on-chip power domain and hence can be
> programmed in SW to safely power collapse and restore power to the
> respective PDs. They are part of a considerable number of recent QCOM
> SoCs (This series adds support for msm8974, msm8916 and apq8084 devices)
> and are part of the Clock control block.
> 
> The series implements support for GDSC using the genpd framework
> modelling these as SW controllable power domains.
> 
> 8916 support has a dependency on the Global Clock controller support [1]
> posted by Georgi Djakov.
> 
> [1] 
> https://lkml.org/lkml/2015/2/25/416
> 
> Rajendra Nayak (3):
>   clk: qcom: gdsc: Prepare common clk probe to register gdscs
>   clk: qcom: gdsc: Add GDSCs in msm8916 GCC
>   clk: qcom: gdsc: Add GDSCs in apq8084 GCC
> 
> Stephen Boyd (3):
>   clk: qcom: Add support for GDSCs
>   clk: qcom: gdsc: Add GDSCs in msm8974 GCC
>   clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
> 
>  drivers/clk/qcom/Kconfig                      |   8 ++
>  drivers/clk/qcom/Makefile                     |   1 +
>  drivers/clk/qcom/common.c                     |  27 +++++-
>  drivers/clk/qcom/common.h                     |   2 +
>  drivers/clk/qcom/gcc-apq8084.c                |  38 ++++++++
>  drivers/clk/qcom/gcc-msm8916.c                |  46 +++++++++
>  drivers/clk/qcom/gcc-msm8974.c                |  14 +++
>  drivers/clk/qcom/gdsc.c                       | 130 ++++++++++++++++++++++++++
>  drivers/clk/qcom/gdsc.h                       |  43 +++++++++
>  drivers/clk/qcom/mmcc-msm8974.c               |  54 +++++++++++
>  include/dt-bindings/clock/qcom,gcc-apq8084.h  |   6 ++
>  include/dt-bindings/clock/qcom,gcc-msm8916.h  |   8 ++
>  include/dt-bindings/clock/qcom,gcc-msm8974.h  |   3 +
>  include/dt-bindings/clock/qcom,mmcc-msm8974.h |   8 ++
>  14 files changed, 387 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/qcom/gdsc.c
>  create mode 100644 drivers/clk/qcom/gdsc.h
> 

You missed a patch who adds appropriate changes in qcom,gcc.txt
(qcom,mmcc.txt), at least #power-domain-cells property should be described.

-- 
regards,
Stan

[PATCH 0/6] Add support for QCOM GDSCs

[Rajendra Nayak]

> On 03/02/2015 09:02 AM, Rajendra Nayak wrote:
>> GDSCs (Global Distributed Switch Controllers) control switches
>> that supply power to an on-chip power domain and hence can be
>> programmed in SW to safely power collapse and restore power to the
>> respective PDs. They are part of a considerable number of recent QCOM
>> SoCs (This series adds support for msm8974, msm8916 and apq8084 devices)
>> and are part of the Clock control block.
>>
>> The series implements support for GDSC using the genpd framework
>> modelling these as SW controllable power domains.
>>
>> 8916 support has a dependency on the Global Clock controller support [1]
>> posted by Georgi Djakov.
>>
>> [1]
>> https://lkml.org/lkml/2015/2/25/416
>>
>> Rajendra Nayak (3):
>>   clk: qcom: gdsc: Prepare common clk probe to register gdscs
>>   clk: qcom: gdsc: Add GDSCs in msm8916 GCC
>>   clk: qcom: gdsc: Add GDSCs in apq8084 GCC
>>
>> Stephen Boyd (3):
>>   clk: qcom: Add support for GDSCs
>>   clk: qcom: gdsc: Add GDSCs in msm8974 GCC
>>   clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
>>
>>  drivers/clk/qcom/Kconfig                      |   8 ++
>>  drivers/clk/qcom/Makefile                     |   1 +
>>  drivers/clk/qcom/common.c                     |  27 +++++-
>>  drivers/clk/qcom/common.h                     |   2 +
>>  drivers/clk/qcom/gcc-apq8084.c                |  38 ++++++++
>>  drivers/clk/qcom/gcc-msm8916.c                |  46 +++++++++
>>  drivers/clk/qcom/gcc-msm8974.c                |  14 +++
>>  drivers/clk/qcom/gdsc.c                       | 130
>> ++++++++++++++++++++++++++
>>  drivers/clk/qcom/gdsc.h                       |  43 +++++++++
>>  drivers/clk/qcom/mmcc-msm8974.c               |  54 +++++++++++
>>  include/dt-bindings/clock/qcom,gcc-apq8084.h  |   6 ++
>>  include/dt-bindings/clock/qcom,gcc-msm8916.h  |   8 ++
>>  include/dt-bindings/clock/qcom,gcc-msm8974.h  |   3 +
>>  include/dt-bindings/clock/qcom,mmcc-msm8974.h |   8 ++
>>  14 files changed, 387 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/qcom/gdsc.c
>>  create mode 100644 drivers/clk/qcom/gdsc.h
>>
>
> You missed a patch who adds appropriate changes in qcom,gcc.txt
> (qcom,mmcc.txt), at least #power-domain-cells property should be
> described.

Right, I also missed adding those in the dts files (for 8974 and 8084)
which caused failures which I caught after I posted these out.
Thanks for taking time to review, I will fix #power-domain-cells and also
address other concerns you had on PATCH 1/6 and 2/6 and post a v2 soon.

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