[PATCH] ARM: l2c: enforce use of cache-level property

[PATCH] ARM: l2c: enforce use of cache-level property

[Florian Fainelli]

Make sure that we can read the "cache-level" property from the L2 cache
controller node, and ensure its value is 2.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
Russell, Linus,

You may have seen that patch earlier, it was part of my attempt
to parse the 'cache-size' and 'cache-sets' properties, and ultimately
Linus' series went it, and this patch was lost ast see.

Thanks!

 arch/arm/mm/cache-l2x0.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c6c7696b8db9..8b933dc43e24 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1648,6 +1648,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	struct device_node *np;
 	struct resource res;
 	u32 cache_id, old_aux;
+	u32 cache_level = 2;
 
 	np = of_find_matching_node(NULL, l2x0_ids);
 	if (!np)
@@ -1680,6 +1681,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!of_property_read_bool(np, "cache-unified"))
 		pr_err("L2C: device tree omits to specify unified cache\n");
 
+	if (of_property_read_u32(np, "cache-level", &cache_level))
+		pr_err("L2C: device tree omits to specify cache-level\n");
+
+	if (cache_level != 2)
+		pr_err("L2C: device tree specifies invalid cache level\n");
+
 	/* Read back current (default) hardware configuration */
 	if (data->save)
 		data->save(l2x0_base);
-- 
2.1.0

[PATCH] ARM: l2c: enforce use of cache-level property

[Linus Walleij]

On Tue, Mar 3, 2015 at 7:55 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:

> Make sure that we can read the "cache-level" property from the L2 cache
> controller node, and ensure its value is 2.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

(...)
> +       if (of_property_read_u32(np, "cache-level", &cache_level))
> +               pr_err("L2C: device tree omits to specify cache-level\n");
> +

Is that really an error? Does ePAPR specify that this must always be
present or what?

> +       if (cache_level != 2)
> +               pr_err("L2C: device tree specifies invalid cache level\n");

This is an error however.

Yours,
Linus Walleij

[PATCH] ARM: l2c: enforce use of cache-level property

[Russell King - ARM Linux]

On Mon, Mar 09, 2015 at 03:42:14PM +0100, Linus Walleij wrote:
> On Tue, Mar 3, 2015 at 7:55 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> 
> > Make sure that we can read the "cache-level" property from the L2 cache
> > controller node, and ensure its value is 2.
> >
> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> 
> (...)
> > +       if (of_property_read_u32(np, "cache-level", &cache_level))
> > +               pr_err("L2C: device tree omits to specify cache-level\n");
> > +
> 
> Is that really an error? Does ePAPR specify that this must always be
> present or what?

See table 3-9.  It appears to be a required property.

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

[PATCH] ARM: l2c: enforce use of cache-level property

[Russell King - ARM Linux]

On Tue, Mar 03, 2015 at 10:55:41AM -0800, Florian Fainelli wrote:
> Make sure that we can read the "cache-level" property from the L2 cache
> controller node, and ensure its value is 2.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> Russell, Linus,
> 
> You may have seen that patch earlier, it was part of my attempt
> to parse the 'cache-size' and 'cache-sets' properties, and ultimately
> Linus' series went it, and this patch was lost ast see.

Can you put it in the patch system please, and I'll get around to it
once at some point during/after I've finished catching up?

Thanks.

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

[PATCH] ARM: l2c: enforce use of cache-level property

[Florian Fainelli]

2015-03-09 9:03 GMT-07:00 Russell King - ARM Linux <linux@arm.linux.org.uk>:
> On Tue, Mar 03, 2015 at 10:55:41AM -0800, Florian Fainelli wrote:
>> Make sure that we can read the "cache-level" property from the L2 cache
>> controller node, and ensure its value is 2.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>> Russell, Linus,
>>
>> You may have seen that patch earlier, it was part of my attempt
>> to parse the 'cache-size' and 'cache-sets' properties, and ultimately
>> Linus' series went it, and this patch was lost ast see.
>
> Can you put it in the patch system please, and I'll get around to it
> once at some point during/after I've finished catching up?

Added as http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8309/1
thanks!
-- 
Florian