From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 10/11] irqchip: gicv3-its: define macros for GITS_CTLR fields
Date: Fri, 6 Mar 2015 16:37:49 +0000 [thread overview]
Message-ID: <1425659870-11832-11-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1425659870-11832-1-git-send-email-marc.zyngier@arm.com>
From: Yun Wu <wuyun.wu@huawei.com>
Define macros for GITS_CTLR fields to avoid using magic numbers.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Yun Wu <wuyun.wu@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-v3.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index ec20d4a..826da70 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1388,7 +1388,7 @@ static int its_probe(struct device_node *node, struct irq_domain *parent)
writeq_relaxed(baser, its->base + GITS_CBASER);
tmp = readq_relaxed(its->base + GITS_CBASER);
writeq_relaxed(0, its->base + GITS_CWRITER);
- writel_relaxed(1, its->base + GITS_CTLR);
+ writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
if ((tmp ^ baser) & GITS_BASER_SHAREABILITY_MASK) {
pr_info("ITS: using cache flushing for cmd queue\n");
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index cbdd440..781974a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -166,6 +166,9 @@
#define GITS_TRANSLATER 0x10040
+#define GITS_CTLR_ENABLE (1U << 0)
+#define GITS_CTLR_QUIESCENT (1U << 31)
+
#define GITS_TYPER_DEVBITS_SHIFT 13
#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
#define GITS_TYPER_PTA (1UL << 19)
--
2.1.4
next prev parent reply other threads:[~2015-03-06 16:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-06 16:37 [PATCH 00/11] Collection of GIC/GICv3 fixes for 4.0 Marc Zyngier
2015-03-06 16:37 ` [PATCH 01/11] irqchip: gicv3-its: Fix ITS CPU init Marc Zyngier
2015-03-06 16:37 ` [PATCH 02/11] irqchip: gicv3-its: Allocate enough memory for the full range of DeviceID Marc Zyngier
2015-03-06 16:37 ` [PATCH 03/11] irqchip: gicv3-its: Iterate over PCI aliases to generate ITS configuration Marc Zyngier
2015-03-06 16:37 ` [PATCH 04/11] irqchip: gicv3-its: Fix unsafe locking reported by lockdep Marc Zyngier
2015-03-06 16:37 ` [PATCH 05/11] irqchip: gic: " Marc Zyngier
2015-03-06 16:37 ` [PATCH 06/11] irqchip: gic-v3: fix out of bounds access to cpu_logical_map Marc Zyngier
2015-03-06 16:37 ` [PATCH 07/11] irqchip: gicv3-its: zero itt before handling to hardware Marc Zyngier
2015-03-06 16:37 ` [PATCH 08/11] irqchip: gicv3-its: use 64KB page as default granule Marc Zyngier
2015-03-06 16:37 ` [PATCH 09/11] irqchip: gicv3-its: add limitation to page order Marc Zyngier
2015-03-06 16:37 ` Marc Zyngier [this message]
2015-03-06 16:37 ` [PATCH 11/11] irqchip: gicv3-its: support safe initialization Marc Zyngier
2015-03-08 5:56 ` [PATCH 00/11] Collection of GIC/GICv3 fixes for 4.0 Jason Cooper
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