[PATCH 0/3] ARM: sun8i: Add SMP and arch-timer support for A23

[PATCH 0/3] ARM: sun8i: Add SMP and arch-timer support for A23

[Chen-Yu Tsai]

Hi Maxime,

This series adds support for SMP and arch-timer for the
A23. This follows our discussion from yesterday about
getting arch-timer support for sun8i and sun9i. I will
post a separate patch for sun9i-a80.

I know some people would like to see arch-timer and SMP
supported with PSCI, but work on this has been slow. So
in the mean time, I thought I'd just post what SMP code
I have.

Feel free to just merge the first patch if you think SMP
can wait.


Regards
ChenYu


Chen-Yu Tsai (3):
  ARM: dts: sun8i: Enable ARM architected timer on A23
  ARM: sun8i: Add SMP support for the Allwinner A23
  ARM: sun8i: dt: Enable A23 SMP support

 Documentation/devicetree/bindings/arm/cpus.txt |  1 +
 arch/arm/boot/dts/sun8i-a23.dtsi               | 16 ++++++
 arch/arm/mach-sunxi/platsmp.c                  | 69 ++++++++++++++++++++++++++
 3 files changed, 86 insertions(+)

-- 
2.1.4

[PATCH 1/3] ARM: dts: sun8i: Enable ARM architected timer on A23

[Chen-Yu Tsai]

The A23 SoC has the architected timer, but the existing firmware from
Allwinner does not set CNTFRQ at all.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a23.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 674d4c5e7ee1..78440dffd678 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -70,6 +70,16 @@
 		};
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-- 
2.1.4

[PATCH 1/3] ARM: dts: sun8i: Enable ARM architected timer on A23

[Maxime Ripard]

On Wed, Mar 18, 2015 at 11:24:00AM +0800, Chen-Yu Tsai wrote:
> The A23 SoC has the architected timer, but the existing firmware from
> Allwinner does not set CNTFRQ at all.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 2/3] ARM: sun8i: Add SMP support for the Allwinner A23

[Chen-Yu Tsai]

The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
control the CPU configuration and the CPU power so that we can
bring up secondary CPUs at boot.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---

We can't use of_io_request_and_map() here, as it will conflict
with PRCM, and leave us without a serial console.

I think a proper way to solve this would be a syscon device or
something like the mfd-simple device posted by Arnd.

---
 Documentation/devicetree/bindings/arm/cpus.txt |  1 +
 arch/arm/mach-sunxi/platsmp.c                  | 69 ++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a95de31..40202d85b132 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -188,6 +188,7 @@ nodes to be present and contain the properties described below.
 			# On ARM 32-bit systems this property is optional and
 			  can be one of:
 			    "allwinner,sun6i-a31"
+			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
 			    "marvell,armada-375-smp"
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 587b0468efcc..e8483ec79d67 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -121,3 +121,72 @@ static struct smp_operations sun6i_smp_ops __initdata = {
 	.smp_boot_secondary	= sun6i_smp_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+
+static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm");
+	if (!node) {
+		pr_err("Missing A23 PRCM node in the device tree\n");
+		return;
+	}
+
+	prcm_membase = of_iomap(node, 0);
+	if (!prcm_membase) {
+		pr_err("Couldn't map A23 PRCM registers\n");
+		return;
+	}
+
+	node = of_find_compatible_node(NULL, NULL,
+				       "allwinner,sun8i-a23-cpuconfig");
+	if (!node) {
+		pr_err("Missing A23 CPU config node in the device tree\n");
+		return;
+	}
+
+	cpucfg_membase = of_iomap(node, 0);
+	if (!cpucfg_membase)
+		pr_err("Couldn't map A23 CPU config registers\n");
+
+}
+
+static int sun8i_smp_boot_secondary(unsigned int cpu,
+				    struct task_struct *idle)
+{
+	u32 reg;
+
+	if (!(prcm_membase && cpucfg_membase))
+		return -EFAULT;
+
+	spin_lock(&cpu_lock);
+
+	/* Set CPU boot address */
+	writel(virt_to_phys(secondary_startup),
+	       cpucfg_membase + CPUCFG_PRIVATE0_REG);
+
+	/* Assert the CPU core in reset */
+	writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
+
+	/* Assert the L1 cache in reset */
+	reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
+	writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
+
+	/* Clear CPU power-off gating */
+	reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
+	writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
+	mdelay(1);
+
+	/* Deassert the CPU core reset */
+	writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
+
+	spin_unlock(&cpu_lock);
+
+	return 0;
+}
+
+struct smp_operations sun8i_smp_ops __initdata = {
+	.smp_prepare_cpus	= sun8i_smp_prepare_cpus,
+	.smp_boot_secondary	= sun8i_smp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops);
-- 
2.1.4

[PATCH 2/3] ARM: sun8i: Add SMP support for the Allwinner A23

[Maxime Ripard]

On Wed, Mar 18, 2015 at 11:24:01AM +0800, Chen-Yu Tsai wrote:
> The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
> control the CPU configuration and the CPU power so that we can
> bring up secondary CPUs at boot.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> 
> We can't use of_io_request_and_map() here, as it will conflict
> with PRCM, and leave us without a serial console.
> 
> I think a proper way to solve this would be a syscon device or
> something like the mfd-simple device posted by Arnd.
> 
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt |  1 +
>  arch/arm/mach-sunxi/platsmp.c                  | 69 ++++++++++++++++++++++++++
>  2 files changed, 70 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 8b9e0a95de31..40202d85b132 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -188,6 +188,7 @@ nodes to be present and contain the properties described below.
>  			# On ARM 32-bit systems this property is optional and
>  			  can be one of:
>  			    "allwinner,sun6i-a31"
> +			    "allwinner,sun8i-a23"
>  			    "arm,psci"
>  			    "brcm,brahma-b15"
>  			    "marvell,armada-375-smp"
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> index 587b0468efcc..e8483ec79d67 100644
> --- a/arch/arm/mach-sunxi/platsmp.c
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -121,3 +121,72 @@ static struct smp_operations sun6i_smp_ops __initdata = {
>  	.smp_boot_secondary	= sun6i_smp_boot_secondary,
>  };
>  CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
> +
> +static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus)
> +{
> +	struct device_node *node;
> +
> +	node = of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm");
> +	if (!node) {
> +		pr_err("Missing A23 PRCM node in the device tree\n");
> +		return;
> +	}
> +
> +	prcm_membase = of_iomap(node, 0);
> +	if (!prcm_membase) {
> +		pr_err("Couldn't map A23 PRCM registers\n");
> +		return;
> +	}
> +
> +	node = of_find_compatible_node(NULL, NULL,
> +				       "allwinner,sun8i-a23-cpuconfig");
> +	if (!node) {
> +		pr_err("Missing A23 CPU config node in the device tree\n");
> +		return;
> +	}
> +
> +	cpucfg_membase = of_iomap(node, 0);
> +	if (!cpucfg_membase)
> +		pr_err("Couldn't map A23 CPU config registers\n");
> +
> +}
> +
> +static int sun8i_smp_boot_secondary(unsigned int cpu,
> +				    struct task_struct *idle)
> +{
> +	u32 reg;
> +
> +	if (!(prcm_membase && cpucfg_membase))
> +		return -EFAULT;
> +
> +	spin_lock(&cpu_lock);
> +
> +	/* Set CPU boot address */
> +	writel(virt_to_phys(secondary_startup),
> +	       cpucfg_membase + CPUCFG_PRIVATE0_REG);

One question I couldn't find any answer to is that does the SMP bit is
set in secondary_startup?

I couldn't find where it was set, but it still looks like the right
thing to do, so I would expect the code to do that.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 2/3] ARM: sun8i: Add SMP support for the Allwinner A23

[Chen-Yu Tsai]

On Wed, Mar 18, 2015 at 6:29 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Wed, Mar 18, 2015 at 11:24:01AM +0800, Chen-Yu Tsai wrote:
>> The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
>> control the CPU configuration and the CPU power so that we can
>> bring up secondary CPUs at boot.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>
>> We can't use of_io_request_and_map() here, as it will conflict
>> with PRCM, and leave us without a serial console.
>>
>> I think a proper way to solve this would be a syscon device or
>> something like the mfd-simple device posted by Arnd.
>>
>> ---
>>  Documentation/devicetree/bindings/arm/cpus.txt |  1 +
>>  arch/arm/mach-sunxi/platsmp.c                  | 69 ++++++++++++++++++++++++++
>>  2 files changed, 70 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 8b9e0a95de31..40202d85b132 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -188,6 +188,7 @@ nodes to be present and contain the properties described below.
>>                       # On ARM 32-bit systems this property is optional and
>>                         can be one of:
>>                           "allwinner,sun6i-a31"
>> +                         "allwinner,sun8i-a23"
>>                           "arm,psci"
>>                           "brcm,brahma-b15"
>>                           "marvell,armada-375-smp"
>> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
>> index 587b0468efcc..e8483ec79d67 100644
>> --- a/arch/arm/mach-sunxi/platsmp.c
>> +++ b/arch/arm/mach-sunxi/platsmp.c
>> @@ -121,3 +121,72 @@ static struct smp_operations sun6i_smp_ops __initdata = {
>>       .smp_boot_secondary     = sun6i_smp_boot_secondary,
>>  };
>>  CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
>> +
>> +static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus)
>> +{
>> +     struct device_node *node;
>> +
>> +     node = of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm");
>> +     if (!node) {
>> +             pr_err("Missing A23 PRCM node in the device tree\n");
>> +             return;
>> +     }
>> +
>> +     prcm_membase = of_iomap(node, 0);
>> +     if (!prcm_membase) {
>> +             pr_err("Couldn't map A23 PRCM registers\n");
>> +             return;
>> +     }
>> +
>> +     node = of_find_compatible_node(NULL, NULL,
>> +                                    "allwinner,sun8i-a23-cpuconfig");
>> +     if (!node) {
>> +             pr_err("Missing A23 CPU config node in the device tree\n");
>> +             return;
>> +     }
>> +
>> +     cpucfg_membase = of_iomap(node, 0);
>> +     if (!cpucfg_membase)
>> +             pr_err("Couldn't map A23 CPU config registers\n");
>> +
>> +}
>> +
>> +static int sun8i_smp_boot_secondary(unsigned int cpu,
>> +                                 struct task_struct *idle)
>> +{
>> +     u32 reg;
>> +
>> +     if (!(prcm_membase && cpucfg_membase))
>> +             return -EFAULT;
>> +
>> +     spin_lock(&cpu_lock);
>> +
>> +     /* Set CPU boot address */
>> +     writel(virt_to_phys(secondary_startup),
>> +            cpucfg_membase + CPUCFG_PRIVATE0_REG);
>
> One question I couldn't find any answer to is that does the SMP bit is
> set in secondary_startup?
>
> I couldn't find where it was set, but it still looks like the right
> thing to do, so I would expect the code to do that.

I don't see it either. The sun8i code is just the sun6i code with the
power clamps removed. And sun6i secondary_startup was removed some time
ago in commit 1146b600044d ("ARM: sunxi: fix build for THUMB2_KERNEL").

ChenYu

[linux-sunxi] Re: [PATCH 2/3] ARM: sun8i: Add SMP support for the Allwinner A23

[maxime.ripard]

Hi Kevin,

On Thu, Mar 19, 2015 at 12:05:06PM +0800, kevin.z.m.zh at gmail.com wrote:
> >> One question I couldn't find any answer to is that does the SMP bit is
> >> set in secondary_startup?
> >>
> >> I couldn't find where it was set, but it still looks like the right
> >> thing to do, so I would expect the code to do that.
> > 
> > I don't see it either. The sun8i code is just the sun6i code with the
> > power clamps removed. And sun6i secondary_startup was removed some time
> > ago in commit 1146b600044d ("ARM: sunxi: fix build for THUMB2_KERNEL").
> > 
> > ChenYu
>
> The SMP bit should be set in the function of "__v7_ca7mp_setup", which is located
> in the file:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mm/proc-v7.S?id=refs/tags/v4.0-rc4
> I'm not sure if this is your discussion.

It is, but I wasn't seeing it called anywhere in the secondary_startup
code path.

I was expecting a direct call, but it looks like it's a dynamic call,
with a function-pointer like call, that is indeed run both in the
kernel entry point and the secondary_startup.

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/kernel/head.S?id=refs/tags/v4.0-rc4#n389

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[linux-sunxi] Re: [PATCH 2/3] ARM: sun8i: Add SMP support for the Allwinner A23

[Chen-Yu Tsai]

Hi Maxime,

On Thu, Mar 19, 2015 at 2:18 AM, maxime.ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Kevin,
>
> On Thu, Mar 19, 2015 at 12:05:06PM +0800, kevin.z.m.zh at gmail.com wrote:
>> >> One question I couldn't find any answer to is that does the SMP bit is
>> >> set in secondary_startup?
>> >>
>> >> I couldn't find where it was set, but it still looks like the right
>> >> thing to do, so I would expect the code to do that.
>> >
>> > I don't see it either. The sun8i code is just the sun6i code with the
>> > power clamps removed. And sun6i secondary_startup was removed some time
>> > ago in commit 1146b600044d ("ARM: sunxi: fix build for THUMB2_KERNEL").
>> >
>> > ChenYu
>>
>> The SMP bit should be set in the function of "__v7_ca7mp_setup", which is located
>> in the file:
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mm/proc-v7.S?id=refs/tags/v4.0-rc4
>> I'm not sure if this is your discussion.
>
> It is, but I wasn't seeing it called anywhere in the secondary_startup
> code path.
>
> I was expecting a direct call, but it looks like it's a dynamic call,
> with a function-pointer like call, that is indeed run both in the
> kernel entry point and the secondary_startup.
>
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/kernel/head.S?id=refs/tags/v4.0-rc4#n389

Are we waiting for Marc's input on this?

ChenYu

[linux-sunxi] Re: [PATCH 2/3] ARM: sun8i: Add SMP support for the Allwinner A23

[maxime.ripard]

On Wed, Mar 25, 2015 at 04:39:08PM -0700, Chen-Yu Tsai wrote:
> Hi Maxime,
> 
> On Thu, Mar 19, 2015 at 2:18 AM, maxime.ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi Kevin,
> >
> > On Thu, Mar 19, 2015 at 12:05:06PM +0800, kevin.z.m.zh at gmail.com wrote:
> >> >> One question I couldn't find any answer to is that does the SMP bit is
> >> >> set in secondary_startup?
> >> >>
> >> >> I couldn't find where it was set, but it still looks like the right
> >> >> thing to do, so I would expect the code to do that.
> >> >
> >> > I don't see it either. The sun8i code is just the sun6i code with the
> >> > power clamps removed. And sun6i secondary_startup was removed some time
> >> > ago in commit 1146b600044d ("ARM: sunxi: fix build for THUMB2_KERNEL").
> >> >
> >> > ChenYu
> >>
> >> The SMP bit should be set in the function of "__v7_ca7mp_setup", which is located
> >> in the file:
> >> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mm/proc-v7.S?id=refs/tags/v4.0-rc4
> >> I'm not sure if this is your discussion.
> >
> > It is, but I wasn't seeing it called anywhere in the secondary_startup
> > code path.
> >
> > I was expecting a direct call, but it looks like it's a dynamic call,
> > with a function-pointer like call, that is indeed run both in the
> > kernel entry point and the secondary_startup.
> >
> > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/kernel/head.S?id=refs/tags/v4.0-rc4#n389
> 
> Are we waiting for Marc's input on this?

Hmm, no, not really, I just forgot about it :)

I'll merge the patches.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 3/3] ARM: sun8i: dt: Enable A23 SMP support

[Chen-Yu Tsai]

Add enable-method property to enable SMP support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a23.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 78440dffd678..b5684a0048b2 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -81,6 +81,7 @@
 	};
 
 	cpus {
+		enable-method = "allwinner,sun8i-a23";
 		#address-cells = <1>;
 		#size-cells = <0>;
 
@@ -650,6 +651,11 @@
 			};
 		};
 
+		cpucfg at 01f01c00 {
+			compatible = "allwinner,sun8i-a23-cpuconfig";
+			reg = <0x01f01c00 0x300>;
+		};
+
 		r_uart: serial at 01f02800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01f02800 0x400>;
-- 
2.1.4

[PATCH 0/3] ARM: sun8i: Add SMP and arch-timer support for A23

[Maxime Ripard]

On Wed, Mar 18, 2015 at 11:23:59AM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
> 
> This series adds support for SMP and arch-timer for the
> A23. This follows our discussion from yesterday about
> getting arch-timer support for sun8i and sun9i. I will
> post a separate patch for sun9i-a80.
> 
> I know some people would like to see arch-timer and SMP
> supported with PSCI, but work on this has been slow. So
> in the mean time, I thought I'd just post what SMP code
> I have.
> 
> Feel free to just merge the first patch if you think SMP
> can wait.

Merged 2 and 3, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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