[PATCH 0/3] ARM: dts: sun6i: Enable cpufreq support for A31/A31s

[PATCH 0/3] ARM: dts: sun6i: Enable cpufreq support for A31/A31s

[Chen-Yu Tsai]

Hi everyone,

This series adds the DT parts of cpufreq support, clock references, thermal
zones and OPPs, for sun6i. This is based on sunxi/for-next (6bcf44d5edfb).
Required (sun4i-ts) driver support is already in v4.0-rc1.

Patch 1 moves the ahb1 assigned-clocks reparenting properties from the dma
controller node to the ahb1 clock node. This matches what we've done for
sun5i and sun7i. The purpose of this is to clock ahb1 from a stable clock
as soon as possible, to prevent hrtimer miscalculation/instability.

Patch 2 adds the clock reference and OPPs for the cpu cluster.

Patch 3 adds the thermal zones for CPU passive (cpufreq limiting) cooling.

I've tested this on my Sinlinx SinA31s (not yet mainlined). The highest
OPP matches the default CPU clock/voltage setting found in mainline
u-boot. However the Mele I7 fex file specifies a slightly higher voltage
for 1008 MHz. If the default setting is not stable enough for the Mele
I7, it should be overridden in the board dts file.

This series does not cover A31/A31s revision D, which seems to have lower
voltage requirements. At the moment no one has seen them.


Regards
ChenYu


Chen-Yu Tsai (3):
  ARM: dts: sun6i: Set PLL6 as parent to AHB1 clock in AHB1 clock node
  ARM: dts: sun6i: Add cpu clock reference and operating points to dtsi
  ARM: dts: sun6i: Add cpu thermal zones to dtsi

 arch/arm/boot/dts/sun6i-a31.dtsi | 59 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 54 insertions(+), 5 deletions(-)

-- 
2.1.4

[PATCH 1/3] ARM: dts: sun6i: Set PLL6 as parent to AHB1 clock in AHB1 clock node

[Chen-Yu Tsai]

On sun6i we already have PLL6 as AHB1 clock's parent. However this was
previously set in the dma controller node, which takes effect when the
dma controller is probed.

We want this to take effect as soon as possible, so hrtimer rate
calculation is correct, and to be sure the AHB1 clock rate remains as
stable as possible.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2a37ee93265e..6d29eab5fe32 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -196,6 +196,14 @@
 			reg = <0x01c20054 0x4>;
 			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 			clock-output-names = "ahb1";
+
+			/*
+			 * Clock AHB1 from PLL6, instead of CPU/AXI which
+			 * has rate changes due to cpufreq. Also the DMA
+			 * controller requires AHB1 clocked from PLL6.
+			 */
+			assigned-clocks = <&ahb1>;
+			assigned-clock-parents = <&pll6 0>;
 		};
 
 		ahb1_gates: clk at 01c20060 {
@@ -381,10 +389,6 @@
 			clocks = <&ahb1_gates 6>;
 			resets = <&ahb1_rst 6>;
 			#dma-cells = <1>;
-
-			/* DMA controller requires AHB1 clocked from PLL6 */
-			assigned-clocks = <&ahb1>;
-			assigned-clock-parents = <&pll6 0>;
 		};
 
 		mmc0: mmc at 01c0f000 {
-- 
2.1.4

[PATCH 2/3] ARM: dts: sun6i: Add cpu clock reference and operating points to dtsi

[Chen-Yu Tsai]

The cpu core is clocked from the "cpu" clock. Add a reference to it
in the first cpu node. Also add "cpu0" label to the node.

The operating points were taken from the a list compiled by Maxime Ripard,
which is based on A31 FEX files from the sunxi-boards repository. Not all
boards have the same settings. The settings in this patch are the ones
shared by A/B/C revisions, plus the default clock setting from u-boot.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 6d29eab5fe32..9a68acc1070f 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -96,10 +96,22 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu0: cpu at 0 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&cpu>;
+			clock-latency = <244144>; /* 8 32k periods */
+			operating-points = <
+				/* kHz    uV */
+				1008000	1200000
+				864000  1200000
+				720000  1100000
+				480000  1000000
+				>;
+			#cooling-cells = <2>;
+			cooling-min-level = <0>;
+			cooling-max-level = <3>;
 		};
 
 		cpu at 1 {
-- 
2.1.4

[PATCH 3/3] ARM: dts: sun6i: Add cpu thermal zones to dtsi

[Chen-Yu Tsai]

The core temperature sensor now supports thermal zones. Add a thermal
zone mapping for the cpus with passive cooling (cpufreq throttling).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 9a68acc1070f..60d912eeb7c7 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -50,6 +50,7 @@
 #include "skeleton.dtsi"
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
@@ -133,6 +134,38 @@
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal {
+			/* milliseconds */
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&rtp>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu_alert0: cpu_alert0 {
+					/* milliCelsius */
+					temperature = <70000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu_crit {
+					/* milliCelsius */
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	memory {
 		reg = <0x40000000 0x80000000>;
 	};
-- 
2.1.4

[PATCH 0/3] ARM: dts: sun6i: Enable cpufreq support for A31/A31s

[Maxime Ripard]

On Thu, Mar 26, 2015 at 05:04:46AM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> This series adds the DT parts of cpufreq support, clock references, thermal
> zones and OPPs, for sun6i. This is based on sunxi/for-next (6bcf44d5edfb).
> Required (sun4i-ts) driver support is already in v4.0-rc1.
> 
> Patch 1 moves the ahb1 assigned-clocks reparenting properties from the dma
> controller node to the ahb1 clock node. This matches what we've done for
> sun5i and sun7i. The purpose of this is to clock ahb1 from a stable clock
> as soon as possible, to prevent hrtimer miscalculation/instability.
> 
> Patch 2 adds the clock reference and OPPs for the cpu cluster.
> 
> Patch 3 adds the thermal zones for CPU passive (cpufreq limiting) cooling.
> 
> I've tested this on my Sinlinx SinA31s (not yet mainlined). The highest
> OPP matches the default CPU clock/voltage setting found in mainline
> u-boot. However the Mele I7 fex file specifies a slightly higher voltage
> for 1008 MHz. If the default setting is not stable enough for the Mele
> I7, it should be overridden in the board dts file.
> 
> This series does not cover A31/A31s revision D, which seems to have lower
> voltage requirements. At the moment no one has seen them.

Applied all three, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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