From: linus.walleij@linaro.org (Linus Walleij)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 07/13 v2] coresight: tmc: let runtime PM handle core clock
Date: Mon, 20 Apr 2015 14:59:00 +0200 [thread overview]
Message-ID: <1429534746-3068-7-git-send-email-linus.walleij@linaro.org> (raw)
In-Reply-To: <1429534746-3068-1-git-send-email-linus.walleij@linaro.org>
This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will uprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.
Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
the clk_prepare_enable() and clk_disable_unprepare() was
called and thus just increase and decreas the refcount by
one, without it reaching zero and actually disabling the
clock. Now the runtime PM callbacks will make sure the PCLK
is properly disabled after probe.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Rebased on the coresight git tree.
- Added Ulf's review tag.
---
drivers/hwtracing/coresight/coresight-tmc.c | 20 +++++---------------
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 7147f3dd363c..8f2e55cc354c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -23,7 +23,7 @@
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/spinlock.h>
-#include <linux/clk.h>
+#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/coresight.h>
#include <linux/amba/bus.h>
@@ -104,7 +104,6 @@ enum tmc_mem_intf_width {
* @dev: the device entity associated to this component.
* @csdev: component vitals needed by the framework.
* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
- * @clk: the clock this component is associated to.
* @spinlock: only one at a time pls.
* @read_count: manages preparation of buffer for reading.
* @buf: area of memory where trace data get sent.
@@ -120,7 +119,6 @@ struct tmc_drvdata {
struct device *dev;
struct coresight_device *csdev;
struct miscdevice miscdev;
- struct clk *clk;
spinlock_t spinlock;
int read_count;
bool reading;
@@ -242,17 +240,14 @@ static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
{
- int ret;
unsigned long flags;
- ret = clk_prepare_enable(drvdata->clk);
- if (ret)
- return ret;
+ pm_runtime_get_sync(drvdata->dev);
spin_lock_irqsave(&drvdata->spinlock, flags);
if (drvdata->reading) {
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- clk_disable_unprepare(drvdata->clk);
+ pm_runtime_put(drvdata->dev);
return -EBUSY;
}
@@ -386,7 +381,7 @@ out:
drvdata->enable = false;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- clk_disable_unprepare(drvdata->clk);
+ pm_runtime_put(drvdata->dev);
dev_info(drvdata->dev, "TMC disabled\n");
}
@@ -700,11 +695,6 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
spin_lock_init(&drvdata->spinlock);
- drvdata->clk = adev->pclk;
- ret = clk_prepare_enable(drvdata->clk);
- if (ret)
- return ret;
-
devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
drvdata->config_type = BMVAL(devid, 6, 7);
@@ -719,7 +709,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
}
- clk_disable_unprepare(drvdata->clk);
+ pm_runtime_put(&adev->dev);
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
drvdata->vaddr = dma_alloc_coherent(dev, drvdata->size,
--
1.9.3
next prev parent reply other threads:[~2015-04-20 12:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-20 12:58 [PATCH 01/13 v2] coresight: etm: print what version of ETM/PTM is detected Linus Walleij
2015-04-20 12:58 ` [PATCH 02/13 v2] coresight: support the TPIU version found in Ux500 Linus Walleij
2015-04-20 12:58 ` [PATCH 03/13 v2] coresight: etm: let runtime PM handle core clock Linus Walleij
2015-04-20 12:58 ` [PATCH 04/13 v2] coresight: tpiu: " Linus Walleij
2015-04-20 12:58 ` [PATCH 05/13 v2] coresight: etb: " Linus Walleij
2015-04-20 12:58 ` [PATCH 06/13 v2] coresight: funnel: " Linus Walleij
2015-04-20 12:59 ` Linus Walleij [this message]
2015-04-20 12:59 ` [PATCH 08/13 v2] coresight: etm: retrieve and handle atclk Linus Walleij
2015-04-20 12:59 ` [PATCH 09/13 v2] coresight: tpiu: " Linus Walleij
2015-04-20 12:59 ` [PATCH 10/13 v2] coresight: etb: " Linus Walleij
2015-04-20 12:59 ` [PATCH 11/13 v2] coresight: funnel: " Linus Walleij
2015-04-20 12:59 ` [PATCH 12/13 v2] coresight: replicator: " Linus Walleij
2015-04-20 14:17 ` Ulf Hansson
2015-04-20 12:59 ` [PATCH 13/13] coresight: document the bindings for the ATCLK Linus Walleij
2015-04-21 14:31 ` Mathieu Poirier
2015-04-22 13:50 ` [PATCH 01/13 v2] coresight: etm: print what version of ETM/PTM is detected Mathieu Poirier
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