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Sat, 25 Apr 2026 14:31:43 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , Subject: [PATCH rc v3 3/5] iommu/arm-smmu-v3: Retain CR0_SMMUEN during kdump device reset Date: Sat, 25 Apr 2026 14:30:48 -0700 Message-ID: <1429cebde1bdc3577ef24ee4f95e64397d538b31.1777150307.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615D:EE_|LV8PR12MB9644:EE_ X-MS-Office365-Filtering-Correlation-Id: 6fd93daa-d9a5-4257-af2a-08dea31212c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|7416014|376014|82310400026|22082099003|56012099003|18002099003|18096099003; X-Microsoft-Antispam-Message-Info: /XTxRgAqP0LmuvwtBrb2rkLUUsNidBF4LPC8lfit1gRXGVFjCHVASgNlmSWUW8k5e2P0QV1nHy9qfU4ulPn4ZAVIARqAKOx/iJJT/qIJy35w6pKQX5+tby9CGLMpCUMT+MjWOYIi3GPe2ALxHWsBFLO743VcgSg1+AsWwXu2rKEJDSU66wwjEPqodgOGQ5KjVw1IvTnzBxqfP23v73ibO6SogTgoLVWRMckNMcSupjJFG4gcEC6SSQHsglcUjPjygp5ep6ayGK4lZ4kopsmuKztlNZZNmStdskAL7O6Z5z2e6pl/M4YMKsvGAZOzys9K9T+pVAIS6I1El4zTqVnnv/xI7yKQjGFVDTKln2z+sSZj3BwrSXCv7IhNTaXtI+6/M1fpq0Bn/GPCOksRg4JwGBfoNlhgrlu31qmEkV56PCQB1UtzTf1V1QmZkxCsbZIdJE9hXwiqPYVb+Cw8NEE4VD6b7Mfi/p5dAs5DIPiTVLqRr1NFkKo+SUa4dPG5donuMESumRCt938oHrpKfbUrhHpYD/aH0EYSJbwVIZPqcGBLvgwd+/knB1KQg6Im8WKmEpYne4d0H6klqeWA+uB1dJW9/Hol+sAxattRMmnz6QYiA+08K1jGyGI6pgS7J0pddMvwTFCGC3cA3My3ExJTyTurHXb5HxDs6C50Mtw/Oj3sxEu8i+XpCY0QW4Nw+8TPcKuomJTcecQ1jPy0EOC10hxjnapmGkJmqDJAsZ0vbd3Nb9sjPH4ar9+LfXEM8SCkMSGu8QqjbZYI+SuDvx2CeA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(7416014)(376014)(82310400026)(22082099003)(56012099003)(18002099003)(18096099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9SRQqZeod9zpO4ctiKUE+0Y5PgZIyshTF/v5xZW2yLFW8YxKK1/ieojfHPJZtM+pd6piZhewWd5ZRrDQp/vYOOtjBuIhQna5zc8aIOmYHrIB1me/pKTDD3OYIWIqQdyPPz0saOa1cOqwqui1o6LlnR73YS/tAsa03R2N8jYpzi+gQZZyKEBoRqG1J9olxB/QIX4mb8abUFMBfG1jxGeNDyKZSr26izwosEktVSuD3mwOJhV/Wia55ERtij5AmLlUkGGadBMhpjKANkoLCseyU1CZ/xXT6r9HXvE9ba+Gi8QXBEXJ2L5iLybnVuQYthrAbzu5GUyODqLPbC2VGJ6mGi5xdxD5fC5FKf4EtFfID6PsiZlZhZ1FguQy0hU8jGm+5rF7tgyz8ZBAEf+vV8S7iBUd7WzuYp5zyUGbJhsK1mDOVuSk3Cuuqn0hHWkEZK2o X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2026 21:31:55.1395 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6fd93daa-d9a5-4257-af2a-08dea31212c0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9644 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260425_143203_268037_5B03B277 X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When ARM_SMMU_OPT_KDUMP_ADOPT is detected, do not disable SMMUEN and skip the CR1/CR2/STRTAB_BASE update sequence in arm_smmu_device_reset(). Those register writes are all CONSTRAINED UNPREDICTABLE while CR0_SMMUEN==1, so leaving them intact lets in-flight DMAs continue to be translated by the adopted stream table. Initialize 'enables' to 0 so it can carry CR0_SMMUEN in kdump case. Then, preserve that when enabling the command queue. Clear latched gerror bits if necessary. Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel") Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 +++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8423bcc4be69e..b6aade469a6b6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5017,11 +5017,28 @@ static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; - u32 reg, enables; + u32 reg, enables = 0; struct arm_smmu_cmdq_ent cmd; - /* Clear CR0 and sync (disables SMMU and queue processing) */ reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); + + /* + * In a kdump case (set when CR0_SMMUEN=1 and !GERROR_SFM_ERR), retain + * CR0_SMMUEN to avoid aborting in-flight DMA, and CR0_ATSCHK to carry + * on the ATS-check policy. + * + * According to spec, updating STRTAB_BASE/CR1/CR2 when CR0_SMMUEN=1 is + * CONSTRAINED UNPREDICTABLE. So, skip those register updates and rely + * on the adopted stream table from the crashed kernel. + */ + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + dev_info(smmu->dev, + "kdump: retaining SMMUEN for in-flight DMA\n"); + enables = reg & (CR0_SMMUEN | CR0_ATSCHK); + goto reset_queues; + } + + /* Clear CR0 and sync (disables SMMU and queue processing) */ if (reg & CR0_SMMUEN) { dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); @@ -5051,12 +5068,36 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Stream table */ arm_smmu_write_strtab(smmu); +reset_queues: + if (smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) { + /* Disable queues since arm_smmu_device_disable() was skipped */ + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to disable queues\n"); + return ret; + } + } + + /* + * GERROR bits are latched. Read after queue disabling so that unhandled + * errors would be visible. Ack everything prior to re-enabling the CMDQ + * as a stale CMDQ_ERR would halt the CMDQ and new command will timeout. + */ + if (is_kdump_kernel()) { + u32 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); + u32 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + + if ((gerror ^ gerrorn) & GERROR_ERR_MASK) + writel(gerror, smmu->base + ARM_SMMU_GERRORN); + } + /* Command queue */ writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); - enables = CR0_CMDQEN; + enables |= CR0_CMDQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); if (ret) { -- 2.43.0